Renesas M16C/60 Series Hardware Manual page 104

Under development
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M16C/6N5 Group
DMA1 request cause select register
b7 b6 b5 b4 b3
Note: The causes of DMA1 requests can be selected by a combination of DMS bit and DSEL3 to DSEL0 bits in the
manner described below.
DSEL3 to DSEL0
0 0 0 0
2
0 0 0 1
2
0 0 1 0
2
0 0 1 1
2
0 1 0 0
2
0 1 0 1
2
0 1 1 0
2
0 1 1 1
2
1 0 0 0
2
1 0 0 1
2
1 0 1 0
2
1 0 1 1
2
1 1 0 0
2
1 1 0 1
2
1 1 1 0
2
1 1 1 1
2
DMAi control register (i = 0, 1)
b7 b6 b5 b4 b3
Note 1: The DMAS bit can be set to "0" by writing "0" in a program. (This bit remains unchanged even if "1" is written.)
Note 2: At least one of the DAD and DSD bits must be "0" (address direction fixed).
Figure 1.12.3 DM1SL Register, DM0CON Register and DM1CON Register
Rev.1.00 2003.05.30 page 90
b2 b1 b0
Symbol
DM1SL
Bit symbol
DSEL0
DSEL1
DMA request cause
select bit
DSEL2
DSEL3
-
Nothing is assigned. When write, set to "0".
(b5-b4)
When read, its content is "0".
DMA request cause
DMS
expansion select bit
Software DMA
DSR
request bit
DMS = 0 (basic cause of request)
Falling edge of INT1 pin
Software trigger
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
Timer B0
Timer B1
Timer B2
UART0 transmit
UART0 receive/ACK0
UART2 transmit
UART2 receive/ACK2
A-D conversion
UART1 transmit/ACK1
b2 b1 b0
Symbol
DM0CON
DM1CON
Bit symbol
Transfer unit bit
DMBIT
select bit
Repeat transfer mode
DMASL
select bit
DMAS DMA request bit
DMAE DMA enable bit
Source address direction
DSD
select bit
Destination address
DAD
direction select bit (Note 2)
-
Nothing is assigned. When write, set to "0".
(b7-b6)
When read, its content is "0".
Address After reset
03BA 00
16 16
Bit name
Refer to note
0 : Basic cause of request
1 : Extended cause of request
A DMA request is generated by setting
this bit to "1" when the DMS bit is "0"
(basic cause) and the DSEL3 to DSEL0
bits are "0001
The value of this bit when read is "0".
DMS = 1 (extended cause of request)
—
—
—
—
—
SI/O3
—
Two edges of INT1 pin
—
—
—
—
—
—
—
—
Address After reset
002C 00000X00
16
003C 00000X00
16
Bit name
0 : 16 bits
1 : 8 bits
0 : Single transfer
1 : Repeat transfer
0 : DMA not requested
1 : DMA requested
0 : Disabled
1 : Enabled
0 : Fixed
(Note 2) 1 : Forward
0 : Fixed
1 : Forward
Function
RW
RW
RW
RW
RW
-
RW
RW
" (software trigger).
2
2
2
Function
RW
RW
RW
RW
(Note 1)
RW
RW
RW
-
DMAC