Renesas M16C/60 Series Hardware Manual page 121

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M16C/6N5 Group
Timer Ai mode register (i = 2 to 4)
(When using two-phase pulse signal processing)
b6 b5 b4 b3 b2
0 1 0 0
Note 1: TCK1 bit is valid for timer A3 mode register. No matter how this bit is set, timers A2 and A4 always operate in
normal processing mode and x4 processing mode, respectively.
Note 2: If two-phase pulse signal processing is desired, following register settings are required:
Set the UDF register's TAiP bit to "1" (two-phase pulse signal processing function enabled).
Set the TRGSR register's TAiTGH and TAiTGL bits to "00
Set the port direction bits for TAi
Figure 1.13.9 TA2MR to TA4MR Registers in Event Counter Mode (when using two-phase pulse
signal processing with timer A2, A3 or A4)
Rev.1.00 2003.05.30 page 107
b1 b0
Symbol
0 1
TA2MR to TA4MR
TMOD0
Operation mode select bit
TMOD1
MR0
To use two-phase pulse signal processing, set this bit to "0".
MR1
To use two-phase pulse signal processing, set this bit to "1"
MR2
To use two-phase pulse signal processing, set this bit to "0".
MR3
Count operation type
TCK0
select bit
Two-phase pulse signal
TCK1 processing operation
select bit
and TAi
IN
Address After reset
0398 to 039A
16 16
Bit name
b1 b0
0 1 : Event counter mode
0 : Reload type
1 : Free-run type
0 : Normal processing operation
1 : Multiply-by-4 processing operation
(Notes 1, 2)
" (TAi pin input).
2 IN
to "0" (input mode).
OUT
00
16
Function
.
Timer A
RW
RW
RW
RW
RW
RW
RW
RW
RW