Renesas M16C/60 Series Hardware Manual page 88

Under development
This document is under development and its contents are subject to change.
M16C/6N5 Group
I Flag
The I flag enables or disables the maskable interrupt. Setting the I flag to "1" (enabled) enables the
maskable interrupt. Setting the I flag to "0" (disabled) disables all maskable interrupts.
IR Bit
The IR bit is set to "1" (interrupt requested) when an interrupt request is generated. Then, when the
interrupt request is accepted and the CPU branches to the corresponding interrupt vector, the IR bit is set
to "0" (interrupt not requested).
The IR bit can be set to "0" in a program. Note that do not write "1" to this bit.
ILVL2 to ILVL0 Bits and IPL
Interrupt priority levels can be set using the ILVL2 to ILVL0 bits.
Table 1.10.3 shows the settings of interrupt priority levels and Table 1.10.4 shows the interrupt priority
levels enabled by the IPL.
The following are conditions under which an interrupt is accepted:
· I flag = 1
· IR bit = 1
· interrupt priority level > IPL
The I flag, IR bit, ILVL2 to ILVL0 bits and IPL are independent of each other. In no case do they affect one
another.
Table 1.10.3 Settings of Interrupt Priority Levels
ILVL2 to ILVL0 bits Interrupt priority level Priority order
000 Level 0 (Interrupt disabled)
2
001 Level 1
2
010 Level 2
2
011 Level 3
2
100 Level 4
2
101 Level 5
2
110 Level 6
2
111 Level 7
2
Rev.1.00 2003.05.30 page 74
Table 1.10.4 Interrupt Priority Levels Enabled
IPL
- 000
2
Low 001
2
010
2
011
2
100
2
101
2
110
2
High 111
2
by IPL
Enabled interrupt priority levels
Interrupt levels 1 and above are enabled
Interrupt levels 2 and above are enabled
Interrupt levels 3 and above are enabled
Interrupt levels 5 and above are enabled
Interrupt levels 5 and above are enabled
Interrupt levels 6 and above are enabled
Interrupt levels 7 and above are enabled
All maskable interrupts are disabled
Interrupts