Renesas M16C/60 Series Hardware Manual page 47

Under development
This document is under development and its contents are subject to change.
M16C/6N5 Group
Example 1
To access the external area indicated by CS
after accessing the external area indicated by CS
The address bus and the chip select signal both change state
between these two cycles.
Access to the external
area indicated by CS
BCLK
Read signal
Data bus
Address bus
CS
i
CS
j
Example 3
To a ccess the external area indicated by CS
after accessing the external area indicated by the same CS
The address bus changes state but t he c hip select signal
does not change state.
Access to the external
area indicated by CS
BCLK
Read signal
Data bus
Address bus
CS
i
Note : These examples show the address bus and chip select signal when accessing areas in two successive cycles. The chip select bus cycle
may be extended more than two cycles depending on a combination of these examples.
Shown above is the case where separate bus is selected and the area is accessed for read without wait states. i = 0 to 3, j = 0 to 3 (not including i, however)
Figure 1.7.2 Example of Address Bus and CS
Rev.1.00 2003.05.30 page 33
in the next cycle
j
.
i
Access to the external
area indicated by CS
i j
Data Data
Address Address
in the next cycle
i
.
i
Access to the same
external area
i
Data Data
Address Address
______
i
Example 2
To access the internal ROM or internal RAM in the next cycle
after accessing the external area indicated by CS
The chip s elect s ignal c hanges state but the address bus
does not change state.
Access to the external
area indicated by CS
BCLK
Read signal
Data bus
Address bus
CS
i
Example 4
Not to access any area (nor instruction prefetch generated)
in the next cycle after accessing the external area indicated
by CS .
i
Neither the address bus nor the chip select signal changes
state between these two cycles.
Access to the external
area indicated by CS
BCLK
Read signal
Data bus
Address bus
CS
i
Signal Output in 1 Mbyte Mode
Bus Control
.
i
Access to the internal
ROM or internal RAM
i
Data
Address
No access
i
Data
Address