Dmac - Renesas M16C/60 Series Hardware Manual

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M16C/6N5 Group

DMAC

The DMAC (Direct Memory Access Controller) allows data to be transferred without the CPU intervention.
Two DMAC channels are included. Each time a DMA request occurs, the DMAC transfers one (8- or 16-bit)
data from the source address to the destination address. The DMAC uses the same data bus as used by
the CPU. Because the DMAC has higher priority of bus control than the CPU and because it makes use of
a cycle steal method, it can transfer one word (16 bits) or one byte (8 bits) of data within a very short time
after a DMA request is generated. Figure 1.12.1 shows the block diagram of the DMAC. Table 1.12.1
shows the DMAC specifications. Figures 1.12.2 to 1.12.4 show the DMAC related-registers.
DMA0 transfer counter reload register TCR0 (16)
DMA0 transfer counter TCR0 (16)
DMA1 transfer counter reload register TCR1 (16)
DMA1 transfer counter TCR1 (16)
Note: Pointer is incremented by a DMA request.
Figure 1.12.1 DMAC Block Diagram
A DMA request is generated by a write to the DSR bit of the DMiSL register (i = 0, 1), as well as by an
interrupt request which is generated by any function specified by the DMS and DSEL3 to DSEL0 bits of the
DMiSL register. However, unlike in the case of interrupt requests, DMA requests are not affected by the I
flag and the interrupt control register, so that even when interrupt requests are disabled and no interrupt
request can be accepted, DMA requests are always accepted. Furthermore, because the DMAC does not
affect interrupts, the IR bit of the interrupt control register does not change state due to a DMA transfer.
A data transfer is initiated each time a DMA request is generated when the DMAE bit = 1 (DMA enabled) of
the DMiCON register. However, if the cycle in which a DMA request is generated is faster than the DMA
transfer cycle, the number of transfer requests generated and the number of times data is transferred may
not match. For details, refer to "DMA Requests".
Rev.1.00 2003.05.30 page 87
Address bus
(addresses 0029 , 0028 )
16 16
(addresses 0039 , 0038 )
16 16
Data bus low-order bits
Data bus high-order bits
DMA0 source pointer SAR0(20)
(addresses 0022
DMA0 destination pointer DAR0 (20)
(addresses 0026
DMA0 forward address pointer (20) (Note)
DMA1 source pointer SAR1 (20)
(addresses 0032
DMA1 destination pointer DAR1 (20)
(addresses 0036
DMA1 forward address pointer (20) (Note)
DMA latch high-order bits DMA latch low-order bits
DMAC
to 0020 )
16 16
to 0024 )
16 16
to 0030 )
16 16
to 0034 )
16 16