Precautions For Timers; Timer A - Renesas M16C/60 Series Hardware Manual

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M16C/6N5 Group

1.7 Precautions for Timers

1.7.1 Timer A

1.7.1.1 Timer A (Timer Mode)
1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the
TAiMR (i = 0 to 4) register and the TAi register before setting the TAiS bit in the TABSR register to
"1" (count starts).
Always make sure the TAiMR register is modified while the TAiS bit remains "0" (count stops)
regardless whether after reset or not.
2. While counting is in progress, the counter value can be read out at any time by reading the TAi
register. However, if the counter is read at the same time it is reloaded, the value "FFFF
Also, if the counter is read before it starts counting after a value is set in the TAi register while not
counting, the set value is read.
3. If a low-level signal is applied to the NMI pin when the IVPCR1 bit = 1 (three-phase output forcible
cutoff by input on NMI pin enabled) of the TB2SC register, the TA1
to a high-impedance state.
1.7.1.2 Timer A (Event Counter Mode)
1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the
TAiMR (i = 0 to 4) register, the TAi register, the UDF register, the ONSF register TAZIE, TA0TGL
and TA0TGH bits and the TRGSR register before setting the TAiS bit in the TABSR register to "1"
(count starts).
Always make sure the TAiMR register, the UDF register, the ONSF register TAZIE, TA0TGL and
TA0TGH bits and the TRGSR register are modified while the TAiS bit remains "0" (count stops)
regardless whether after reset or not.
2. While counting is in progress, the counter value can be read out at any time by reading the TAi
register. However, "FFFF
When setting TAi register to a value during a counter stop, the setting value can be read before a
counter starts counting. Also, if the counter is read before it starts counting after a value is set in
the TAi register while not counting, the set value is read.
3. If a low-level signal is applied to the NMI pin when the IVPCR1 bit = 1 (three-phase output forcible
cutoff by input on NMI pin enabled) of the TB2SC register, the TA1
to a high-impedance state.
Rev.1.00 2003.05.30 page 9
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" can be read in underflow, while reloading, and "0000
16
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1.7 Precautions for Timers
" is read.
16
, TA2 and TA4 pins go
OUT OUT OUT
" in overflow.
16
, TA2 and TA4 pins go
OUT OUT OUT