Normal Mode - Renesas M16C/60 Series Hardware Manual

Under development
This document is under development and its contents are subject to change.
M16C/6N5 Group
Figure 1.8.12 shows the state transition from normal operation mode to stop mode and wait mode. Figure
1.8.13 shows the state transition in normal operation mode.
Table 1.8.7 shows a state transition matrix describing allowed transition and setting. The vertical line shows
current state and horizontal line show state after transition.
All oscillators stopped
Stop mode
CM07=0
CM06=1
CM05=0
CM11=0 Stop mode
CM10=1
(Note 3)
Stop mode
Stop mode
CM05, CM06, CM07 : CM0 register's bits
CM10, CM11
Note 1: Do not go directly from PLL operation mode to wait or stop mode.
Note 2: PLL operation mode can be entered from high speed mode. Similarly, PLL operation mode can be changed back to high
speed mode.
Note 3: Write to the CM0 register and CM1 register simultaneously by accessing in word unit while CM21 = 0 (ring oscillator turned off).
Note 4: The ring oscillator clock divided by 8 provides the CPU clock.
Note 5: Before entering stop mode, be sure to set the CM20 bit in the CM2 register to "0" (oscillation stop, re-oscillation detection function
disabled).
Figure 1.8.12 State Transition to Stop Mode and Wait Mode
Rev.1.00 2003.05.30 page 61
CM10=1
(Note 5)
Interrupt
Interrupt
CM10=1
(Note 5)
When
low power
When
dissipation
low-
mode
speed
mode
CM10=1
(Note 5)
Low-speed, low power
dissipation mode
Interrupt
CM10=1
(Note 5)
Ring oscillator, Ring oscillator
Interrupt
(Note 4)
: CM1 register's bits
Reset
Medium-speed mode
(divided-by-8 mode)
High-speed, medium-
speed mode
(Notes 1, 2)
PLL operation
mode
dissipation mode

Normal mode

Clock Generation Circuit
CPU operation stopped
WAIT
instruction
Wait mode
Interrupt
WAIT
instruction
Wait mode
Interrupt
WAIT
instruction
Wait mode
Interrupt
WAIT
instruction
Wait mode
Interrupt