Precautions For Programmable I/O Ports - Renesas M16C/60 Series Hardware Manual

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M16C/6N5 Group

1.12 Precautions for Programmable I/O Ports

1. If a low-level signal is applied to the NMI pin when the TB2SC register IVPCR1 bit = "1" (three-phase
output forcible cutoff by input on NMI pin enabled), the P7
impedance state.
2. Setting the SM32 bit in the S3C register to "1" causes the P9
3. The input threshold voltage of pins differs between programmable input/output ports and peripheral
functions.
Therefore, if any pin is shared by a programmable input/output port and a peripheral function and the
input level at this pin is outside the range of recommended operating conditions V
"high" nor "low"), the input level may be determined differently depending on which side—the programmable
input/output port or the peripheral function—is currently selected.
Rev.1.00 2003.05.30 page 21
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1.12 Precautions for Programmable I/O Ports
to P7 , P8 and P8 pins go to a high-
2 5 0 1
pin to go to a high-impedance state.
2
and V (neither
IH IL