Renesas M16C/60 Series Hardware Manual page 57

Under development
This document is under development and its contents are subject to change.
M16C/6N5 Group
CM04
CM10=1 S Q
(stop mode)
R
S Q
WAIT instruction R
RESET
Software reset
NMI
Interrupt request level
judgment output
CM02, CM04, CM05, CM06, CM07 : CM0 register's bits
CM10, CM11, CM16, CM17
PCLK0, PCLK1
CM21, CM27
CCLK0 to CCLK2
Oscillation stop, re-oscillation detection circuit
Pulse generation circuit
for clock edge detection
Main clock
and charge,
discharge control
PLL frequency synthesizer
Main clock
Figure 1.8.1 Clock Generation Circuit
Rev.1.00 2003.05.30 page 43
Sub clock oscillation circuit
X X
CIN COUT
CM21
Ring oscillator
Oscillation stop,
re-oscillation
detection circuit
X X
IN OUT
PLL frequency
synthesizer
PLL clock
Main clock
1
Main clock
CM05 0
oscillation circuit
: CM1 register's bits
: PCLKR register's bits
: CM2 register's bits
: CCLKR register's bits
CM27 = 0
Charge,
discharge
circuit
CM27 = 1
Programmable
counter
Phase
comparator
I/O ports
Sub clock
Ring oscillator
clock
a
CM21=1
CM21=0
CM11
CM02
b
1/2 1/2
a
1/2
CM06=0
CM17-CM16=01
CM06=0
CM17-CM16=00
2
Reset
Oscillation stop
generation
detection reset
circuit
Oscillation stop,
re-oscillation detection
interrupt generating
circuit
Voltage
Charge
control
pump oscillator
(VCO)
Internal
lowpass filter
Clock Generation Circuit
CM01-CM00=00
2
PM01-PM00=00 , CM01-CM00=01
2 2
PM01-PM00=00 , CM01-CM00=10
2 2
PM01-PM00=00
CM01-CM00=11
f
C32
1/32
f
CAN0
By CCLK0,1 and 2
PCLK0=1
PCLK0=0
PCLK0=1
PCLK0=0
PCLK1=1
PCLK1=0
b c d e f
CM07=0
g
Divider
CPU clock
CM07=1
c d e f
1/2 1/2 1/2
1/32
1/4 1/8 1/16
CM06=0
CM17-CM16=11
2
CM06=1
CM06=0
CM17-CM16=10
2 g
2
Details of divider
Oscillation stop,
re-oscillation detection
interrupt signal
CM21 switch signal
1/2 PLL clock
CLK
OUT
,
2
2
f
AD
BCLK