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M16C/6N5 Group
Priority level of each interrupt
UART1 reception, ACK1
UART0 reception, ACK0
UART2 reception, ACK2
UART1 transmission, NACK1
UART0 transmission, NACK0
A-D conversion, Key input
UART2 bus collision detection
Timer B4, UART1 bus collision detection
CAN0 successful reception
UART2 transmission, NACK2
Timer B3, UART0 bus collision detection
CAN0 successful transmission
Oscillation stop and re-oscillation detection
Figure 1.10.10 Interrupts Priority Select Circuit
Rev.1.00
2003.05.30
page 79
Level 0
(initial value)
INT1
Timer B2
Timer B0
Timer A3
Timer A1
INT2
INT0
Timer B1
Timer A4
Timer A2
Timer A0
DMA1
INT5
INT3
CAN0 error
DMA0
SI/O3, INT4
Timer B5
CAN0 wake-up
IPL
I flag
Address match
Watchdog timer
DBC
NMI
Highest
Priority of peripheral function interrupts
(if priority levels are same)
Lowest
Interrupt request level resolution output
to clock generation circuit (Figure 1.8.1)
Interrupt request accepted
Interrupts
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