Renesas M16C/60 Series Hardware Manual page 161

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M16C/6N5 Group
(c) Continuous Receive Mode
When the UiRRM bit (i = 0 to 2) = 1 (continuous receive mode), the UiC1 register's TI bit is set to "0"
(data present in UiTB register) by reading the UiRB register. In this case, i.e., UiRRM bit = 1, do not
write dummy data to the UiTB register in a program. The U0RRM and U1RRM bits are the UCON
register bit 2 and bit 3, respectively, and the U2RRM bit is the U2C1 register bit 5.
(d) Serial Data Logic Switching Function
When the UiC1 register (i = 0 to 2)'s UiLCH bit = 1 (reverse), the data written to the UiTB register has
its logic reversed before being transmitted. Similarly, the received data has its logic reversed when
read from the UiRB register. Figure 1.15.12 shows serial data logic.
Figure 1.15.12 Serial Data Logic Switching
(e) Transfer Clock Output From Multiple Pins (UART1)
Use the UCON register's CLKMD1 to CLKMD0 bits to select one of the two transfer clock output pins.
Figure 1.15.13 shows the transfer clock output from the multiple pins function usage. This function can
be used when the selected transfer clock for UART1 is an internal clock.
Figure 1.15.13 Transfer Clock Output From Multiple Pins
Rev.1.00 2003.05.30 page 147
(1) When the UiC1 register's UiLCH bit = 0 (no reverse)
"H"
Transfer clock
"L"
TxD "H"
i
D0 D1
(no reverse)
"L"
(2) When the UiC1 register's UiLCH bit = 1 (reverse)
"H"
Transfer clock
"L"
TxD
"H"
i
D0 D1
(reverse)
"L"
i = 0 to 2
* This applies to the case where the UiC0 register's CKPOL bit = 0
(transmit data output at the falling edge and the receive data
taken in at the rising edge of the transfer clock) and the UFORM
bit = 0 (LSB first).
Microcomputer
T D (P6 )
X 1 7
CLKS (P6 )
1 4
CLK (P6 )
1 5
Transfer enabled
when the UCON
register's
CLKMD0 bit = 0
* This applies to the case where the U1MR register's CKDIR bit
= 0 (internal clock) and the UCON register's CLKMD1 bit = 1
(transfer clock output from multiple pins).
Serial I/O (Clock Synchronous Serial I/O Mode)
D2 D3 D4 D5 D6 D7
D2 D3 D4 D5 D6 D7
IN IN
CLK CLK
Transfer enabled
when the UCON
register's
CLKMD0 bit = 1