Interrupts And Interrupt Vector - Renesas M16C/60 Series Hardware Manual

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M16C/6N5 Group

Interrupts and Interrupt Vector

One interrupt vector consists of 4 bytes. Set the start address of each interrupt routine in the respective
interrupt vectors. When an interrupt request is accepted, the CPU branches to the address set in the
corresponding interrupt vector. Figure 1.10.2 shows the interrupt vector.
Figure 1.10.2 Interrupt Vector
• Fixed Vector Tables
The fixed vector tables are allocated to the addresses from FFFDC
fixed vector tables. In the flash memory version of microcomputer, the vector addresses (H) of fixed
vectors are used by the ID code check function. For details, refer to "Functions to Prevent Flash
Memory from Rewriting".
Table 1.10.1 Fixed Vector Tables
Interrupt source
Undefined instruction FFFDC
Overflow
BRK instruction
Address match
Single step (Note)
Oscillation stop and
re-oscillation detection,
Watchdog timer
_________
DBC (Note)
________
NMI
Reset
Note: Do not normally use this interrupt because it is provided exclusively for use by development support
tools.
Rev.1.00 2003.05.30 page 70
MSB
Vector address (L)
Vector address (H)
Vector table addresses
Address (L) to address (H)
to FFFDF Interrupt on UND instruction
16 16
FFFE0 to FFFE3 Interrupt on INTO instruction
16 16
FFFE4 to FFFE7 If the contents of address FFFE7
16 16
is FF
from the address shown by the
vector in the relocatable vector table.
FFFE8 to FFFEB
16 16
FFFEC to FFFEF
16 16
FFFF0 to FFFF3
16 16
FFFF4 to FFFF7
16 16
FFFF8 to FFFFB
16 16
FFFFC to FFFFF
16 16
Low address
Medium address
0 0 0 0 High address
0 0 0 0 0 0 0 0
to FFFFF
16
Remarks
, program execution starts
16
Interrupts
LSB
. Table 1.10.1 lists the
16
Reference
M16C/60, M16C/20
series software manual
16
Address match interrupt
Clock generation circuit
Watchdog timer
________
NMI interrupt
Reset