Renesas M16C/60 Series Hardware Manual page 268

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M16C/6N5 Group
Memory Expansion Mode and Microprocessor Mode
(
For 2-wait setting and external area access
Read timing
BCLK
CSi
ADi
BHE
t
d(BCLK-ALE)
25ns.max
ALE
RD
DBi
Hi-Z
Write timing
BCLK
CSi
ADi
BHE
t
d(BCLK-ALE)
25ns.max
ALE
WR, WRL
WRH
DB
1
tcyc =
f(BCLK)
Measuring conditions :
V = 5 V
CC
Input timing voltage : V
Output timing voltage : V
Figure 1.21.6 Timing Diagram (5)
Rev.1.00 2003.05.30 page 254
)
tcyc
t
d(BCLK-CS)
25ns.max
t
d(BCLK-AD)
25ns.max
t
h(BCLK-ALE)
-4ns.min
t
d(BCLK-RD)
25ns.max
t
ac2(RD-DB)
(2.5 ✕ tcyc-45)ns.max
tcyc
t
d(BCLK-CS)
25ns.max
t
d(BCLK-AD)
25ns.max
t
h(BCLK-ALE)
-4ns.min
t
d(BCLK-WR)
25ns.max
t
d(BCLK-DB)
40ns.max
Hi-Z
t
d(DB-WR)
(1.5 ✕ tcyc-40)ns.min
= 0.8 V, V = 2.0 V
IL IH
= 0.4 V, V = 2.4 V
OL OH
t
h(BCLK-CS)
4ns.min
t
h(BCLK-AD)
4ns.min
t
h(RD-AD)
0ns.min
t
h(BCLK-RD)
0ns.min
t t
SU(DB-RD) h(RD-DB)
40ns.min
0ns.min
t
h(BCLK-CS)
4ns.min
t
h(BCLK-AD)
4ns.min
t
h(WR-AD)
(0.5 ✕ tcyc-10)ns.min
t
h(BCLK-WR)
0ns.min
t
h(BCLK-DB)
4ns.min
t
h(WR-DB)
(0.5 ✕ tcyc-10)ns.min
Electrical Characteristics