Renesas M16C/60 Series Hardware Manual page 62

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M16C/6N5 Group
Processor mode register 2 (Note 1)
b7 b6 b5 b4 b3 b2
0 0
Note 1: Write to this register after setting the PRC1 bit of PRCR register to "1" (write enable).
Note 2: This bit can only be rewritten while the PLC07 bit is "0" (PLL turned off). Also, to select a 16 MHz or higher
PLL clock, set this bit to "0" (2 waits). Note that if the clock source for the CPU clock is to be changed from
the PLL clock to another, the PLC07 bit must be set to "0" before setting the PM20 bit.
Note 3: Once this bit is set to "1", it cannot be set to "0" in a program.
Note 4: Setting the PM22 bit to "1" results in the following conditions:
The ring oscillator starts oscillating, and the ring oscillator clock becomes the watchdog timer count source.
The CM10 bit of CM1 register is disabled against write. (Writing a "1" has no effect, nor is stop mode entered.)
The watchdog timer does not stop when in wait mode or hold state.
Figure 1.8.7 PM2 Register
Rev.1.00 2003.05.30 page 48
Symbol
b1 b0
0 PM2
Bit symbol
Specifying wait when
accessing SFR at PLL
PM20
operation
-
Reserved bit
(b1)
WDT count source
PM22
protective bit (Notes 3, 4)
-
Reserved bit
(b4-b3)
- Nothing is assigned. When write, set to "0".
(b7-b5)
When read, its content is indeterminate.
Address After reset
001E XXX00000
16
Bit name
0 : 2 waits
1 : 1 wait
(Note 2)
Set to "0"
0 : CPU clock is used for the
watchdog timer count source
1 : Ring oscillator clock is used for
the watchdog timer count source
Set to "0"
Clock Generation Circuit
2
Function
RW
RW
RW
RW
RW
-