Renesas M16C/60 Series Hardware Manual page 265

Under development
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M16C/6N5 Group
Memory Expansion Mode and Microprocessor Mode
(Effective for setting with wait)
BCLK
RD
(Separate bus)
WR, WRL, WRH
(Separate bus)
RD
(Multiplexed bus)
WR, WRL, WRH
(Multiplexed bus)
RDY input
(Common to setting with wait and setting without wait)
BCLK
HOLD input
HLDA output
P0, P1, P2,
P3, P4,
P5 to P5
0 2
Note: The above pins are set to high-impedance regardless of the input level of the BYTE pin,
PM06 bit of PM0 register and PM11 bit of PM1 register.
Measuring conditions :
V = 5 V
CC
Input timing voltage : Determined with V
Output timing voltage: Determined with V
Figure 1.21.3 Timing Diagram (2)
Rev.1.00 2003.05.30 page 251
tsu(RDY—BCLK)
t t
su(HOLD—BCLK) h(BCLK—HOLD)
t
d(BCLK—HLDA)
t
d(BCLK—HLDA)
Hi—Z
= 1.0 V, V = 4.0 V
IL IH
= 2.5 V, V = 2.5 V
OL OH
Electrical Characteristics
th(BCLK—RDY)