Renesas M16C/60 Series Hardware Manual page 153

Under development
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M16C/6N5 Group
UART transmit/receive control register 2
b7 b6 b5 b4 b3 b2 b1
Note: When using multiple transfer clock output pins, make sure the following conditions are met:
U1MR register's CKDIR bit = 0 (internal clock)
UARTi special mode register (i = 0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
0
Note 1: The BBS bit is set to "0" by writing "0" in a program. (Writing "1" has no effect.).
Note 2: Underflow signal of timer A3 in UART0, underflow signal of timer A4 in UART1, underflow signal of timer A0 in UART2.
Note 3: When a transfer begins, the SSS bit is set to "0" (Not synchronized to RxD
Figure 1.15.6 UCON Register and U0SMR to U2SMR Registers
Rev.1.00 2003.05.30 page 139
b0
Symbol Address
UCON
Bit
Bit name
symbol
UART0 transmit
U0IRS
interrupt cause select bit
UART1 transmit
U1IRS
interrupt cause select bi t
UART0 continuous
U0RRM
receive mode enable bit
UART1 continuous
U1RRM
receive mode enable bit
UART1 CLK/CLKS
CLKMD0
select bit 0
UART1 CLK/CLKS
CLKMD1
select bit 1 (Note)
Separate UART0
RCSP
CTS/RTS bit
Nothing is assigned. When write, set to "0".
(b7)
When read, its content is indeterminate.
Symbol
U0SMR to U2SMR 01EF
Bit
Bit name
symbol
2
IICM I C mode select bit
Arbitration lost detecting
ABC
flag control bit
BBS Bus busy flag
Reserved bit
(b3)
Bus collision detect
ABSCS
sampling clock select bit
Auto clear function
ACSE
select bit of transmit
enable bit
Transmit start condition
SSS
select bit
Nothing is assigned. When write, set to "0".
(b7)
When read, its content is indeterminate.
After reset
03B0 X0000000
16 2
Function
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed (TXEPT = 1)
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed (TXEPT = 1)
0 : Continuous receive mode disabled
1 : Continuous receive mode enabled
0 : Continuous receive mode disabled
1 : Continuous receive mode enabled
Effective when CLKMD1 = 1
0 : Clock output from CLK1
1 : Clock output from CLKS1
0 : CLK output is only CLK1
1 : Transfer clock output from multiple pins function
selected
0 : CTS/RTS shared pin
1 : CTS/RTS separated (CTS
Address After reset
, 01F3 , 01F7 X0000000
16 16 16
0 : Other than I 2 C mode
2
1 : I C mode
0 : Update per bit
1 : Update per byte
0 : STOP condition detected
1 : START condition detected (busy)
Set to "0"
0 : Rising edge of transfer clock
1 : Underflow signal of timer Aj (Note 2)
0 : No auto clear function
1 : Auto clear at occurrence of bus collision
0 : Not synchronized to RxD
1 : Synchronized to RxD
i
).
i
supplied from the P6 pin)
0 4
2
Function
i
(Note 3)
Serial I/O
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
(Note1)
RW
RW
RW
RW