Renesas M16C/60 Series Hardware Manual page 188

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M16C/6N5 Group
(1) Transmission
Transfer clock
"1"
U2C1 register
TE bit
"0"
"1"
U2C1 register
TI bit
"0"
TxD
2
Parity error signal sent
back from receiver
RxD pin level
2
(Note)
"1"
U2C0 register
TXEPT bit
"0"
S2TIC register "1"
IR bit
"0"
The above timing diagram applies to the case where data is
transferred in the direct format.
U2MR register STPS bit = 0 (1 stop bit)
U2MR register PRY bit = 1 (even parity)
U2C0 register UFORM bit = 0 (LSB first)
U2C1 register U2LCH bit = 0 (no reverse)
U2C1 register U2IRS bit = 1 (transmit is completed)
Note: Because TxD and RxD
2
from receiver.
(2) Reception
Transfer clock
"1"
U2C1 register
RE bit
"0"
Transmitter's
transmit waveform
TxD
2
RxD pin level
2
(Note)
U2C0 register "1"
RI bit
"0"
S2RIC register
"1"
IR bit
"0"
The above timing diagram applies to the case where data is
received in the direct format.
U2MR register STPS bit = 0 (1 stop bit)
U2MR register PRY bit = 1 (even parity)
U2C0 register UFORM bit = 0 (LSB first)
U2C1 register U2LCH bit = 0 (no reverse)
U2C1 register U2IRS bit = 1 (transmit is completed)
Note: Because TxD and RxD
2
error signal received.
Figure 1.15.30 Transmit and Receive Timing in SIM Mode
Rev.1.00 2003.05.30 page 174
Tc
Write data to U2TB register
Start
bit
ST D D D D D D D
0 1 2 3 4 5 6
ST
D D D D D D D
0 2 3
1 4 5 6
The IR bit is set to "1" at the
falling edge of transfer clock
are connected, this is composite waveform consisting of the TxD
2
Tc
Start
bit
ST D D D D D D D
0 1 2 3 4 5 6
ST D
D D D D D D
0 1 2 3 4
5 6
are connected, this is composite waveform consisting of the transmitter's transmit waveform and the parity
2
Transferred from U2TB register to UART2 transmit register
Parity Stop
bit bit
D P SP ST D D D D
7 0 1 2
An "L" level returns due to the
occurrence of a parity error.
D ST
P SP D D D D
7 0 2
1
The level is detected by the
interrupt routine.
Set to "0" when interrupt request is accepted, or set to "0" in a program
Tc = 16 (n + 1) / fi or 16 (n + 1) / f
fi : frequency of U2BRG count source (f
f EXT : frequency of U2BRG count source (external clock)
n : value set to U2BRG
output and the parity error signal sent back
2
Parity Stop
bit
bit
D P SP ST D D D
7 0 1 2
An "L" level is output from TxD
the occurrence of a parity error
D ST
P SP D D D
7 0 1 2
Read the U2RB register
Set to "0" when interrupt request is accepted, or set to "0" in a program
Tc = 16 (n + 1) / fi or 16 (n + 1) / f
fi : frequency of U2BRG count source (f
f : frequency of U2BRG count source (external clock)
EXT
n : value set to U2BRG
Serial I/O (Special Modes)
D D D D P
3 4 5 6 7
SP
D
D D D P
3 7
4 5 6
SP
The level is
detected by the
interrupt routine.
EXT
, f , f , f
1SIO 2SIO 8SIO 32SIO
SP
D D D D D P
3 4 5 6 7
due to
2
D D
D D D P
3 4 7
5 6
SP
Read the U2RB register
EXT
, f , f , f )
1SIO 2SIO 8SIO 32SIO
)