Renesas M16C/60 Series Hardware Manual page 60

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M16C/6N5 Group
Oscillation stop detection register (Note 1)
b7 b6 b5 b4 b3 b2
0 0
Note 1: Write to this register after setting the PRC0 bit of PRCR register to "1" (write enable).
Note 2: The CM20, CM21 and CM27 bits do not change at oscillation stop detection reset.
Note 3: Set the CM20 bit to "0" (disable) before entering stop mode. After exiting stop mode, set the CM20 bit
back to "1" (enable).
Note 4: Set the CM20 bit to "0" (disable) before setting the CM05 bit of CM0 register
Note 5: When the CM20 bit is "1" (oscillation stop, re-oscillation detection function enabled), the CM27 bit is "1"
(oscillation stop, re-oscillation detection interrupt), and the CPU clock source is the main clock, the CM21
bit is set to "1" (ring oscillator clock) if the main clock stop is detected.
Note 6: If the CM20 bit is "1" and the CM23 bit is "1" (main clock turned off), do not set the CM21 bit to "0".
Note 7: Effective when the CM07 bit of CM0 register is "0".
Note 8: Where the CM20 bit is "1" (oscillation stop, re-oscillation detection function enabled), the CM27 bit is "1"
(oscillation stop, re-oscillation detection interrupt), and the CM11 bit is "1" (the CPU clock source is PLL
clock), the CM21 bit remains unchanged even when main clock stop is detected. If the CM22 bit is "0"
under these conditions, oscillation stop, re-oscillation detection interrupt generate at main clock stop detection;
it is, therefore, necessary to set the CM21 bit to "1" (ring oscillator clock) inside the interrupt routine.
Note 9: This bit is set to "1" when the main clock is detected to have stopped and when the main clock is detected
to have restarted oscillating. When this bit changes state from "0" to "1", an oscillation stop, re-oscillation
detection interrupt request is generated. Use this bit in an interrupt routine to discriminate the causes of
interrupts between the oscillation stop, re-oscillation detection interrupt and the watchdog timer interrupt.
This bit is set to "0" by writing "0" in a program. (Writing "1" has no effect. Nor is it set to "0" by an oscillation
stop, re-oscillation detection interrupt request acknowledged.)
If an oscillation stop or a re-oscillation is detected when the CM22 bit = 1, no oscillation stop and re-oscillation
detection interrupt requests are generated.
Note 10: Read the CM23 bit in an oscillation stop, re-oscillation detection interrupt handling routine to determine
the main clock status.
Note 11: When the CM21 bit = 0 (ring oscillator turned off) and the CM05 bit = 1 (main clock turned off), the CM06
bit is fixed to "1" (divide-by-8 mode) and the CM15 bit is fixed to "1" (drive capability High).
Figure 1.8.4 CM2 Register
Rev.1.00 2003.05.30 page 46
b1 b0
Symbol
CM2
Bit symbol
Oscillation stop, re-oscillation
detection enable bit
CM20
System clock select bit 2
CM21
(Notes 2, 5, 6, 7, 8, 11)
Oscillation stop, re-oscillation
CM22
detection flag
X monitor flag (Note 10)
CM23
IN
-
Reserved bit
(b5-b4)
Nothing is assigned. When write, set to "0".
-
When read, its content is indeterminate.
(b6)
Operation select bit
(behavior if oscillation stop,
CM27
re-oscillation is detected)
Address After reset
000C 0X00X000
16
Bit name
0 : Oscillation stop, re-oscillation
detection function disabled
1 : Oscillation stop, re-oscillation
(Notes 2, 3, 4)
detection function enabled
0 : Main clock or PLL clock
(Ring oscillator turned off)
1 : Ring oscillator clock
(Ring oscillator oscillating)
0 : Main clock stop, re-oscillation
not detected
1 : Main clock stop, re-oscillation
(Note 9)
detected
0 : Main clock oscillating
1 : Main clock turned off
Set to "0"
0 : Oscillation stop detection reset
1 : Oscillation stop, re-oscillation
detection interrupt
(Note 2)
Clock Generation Circuit
(Note 2)
2
Function
RW
RW
RW
RW
RO
RW
-
RW