Renesas M16C/60 Series Hardware Manual page 58

Under development
This document is under development and its contents are subject to change.
M16C/6N5 Group
System clock control register 0 (Note 1)
b7 b6 b5 b4 b3 b2
Note 1: Write to this register after setting the PRC0 bit of PRCR register to "1" (write enable).
Note 2: The f clock does not stop. During low speed or low power dissipation mode, do not set this bit to "1"
C32
(peripheral clock turned off when in wait mode).
Note 3: The CM03 bit is set to "1" (high) when the CM04 bit is set to "0" (I/O port) or the microcomputer goes to
stop mode.
Note 4: To use a sub clock, set this bit to "1". Also make sure ports P8
pull-ups.
Note 5: This bit is provided to stop the main clock when the low power dissipation mode or ring oscillator low power
dissipation mode is selected. This bit cannot be used for detection as to whether the main clock stopped
or not. To stop the main clock, the following setting is required:
(1) Set the CM07 bit to "1" (sub clock select) or the CM21 bit of CM2 register to "1" (ring oscillator select)
with the sub clock stably oscillating.
(2) Set the CM20 bit of CM2 register to "0" (oscillation stop, re-oscillation detection function disabled).
(3) Set the CM05 bit to "1" (stop).
Note 6: To use the main clock as the clock source for the CPU clock, follow the procedure below.
(1) Set the CM05 bit to "0" (oscillate)
(2) Wait until t
(3) Set the CM11, CM21 and CM07 bits all to "0".
Note 7: When the CM21 bit = 0 (ring oscillator turned off) and the CM05 bit = 1 (main clock turned off), the CM06
bit is fixed to "1" (divide-by-8 mode) and the CM15 bit is fixed to "1" (drive capability High).
Note 8: During external clock input, only the clock oscillation buffer is turned off and clock input is accepted if the
sub clock is not selected as a CPU clock.
Note 9: When CM05 bit is set to "1", the X
remains connected, the X
Note 10: When entering stop mode from high- or middle-speed mode, ring oscillator mode or ring oscillator low power
mode, the CM06 bit is set to "1" (divide-by-8 mode).
Note 11: After setting the CM04 bit to "1" (X
before switching the CM07 bit from "0" to "1" (sub clock).
Note 12: To return from ring oscillator mode to high-speed or middle-speed mode, set the CM06 and CM15 bits
both to "1".
Figure 1.8.2 CM0 Register
Rev.1.00 2003.05.30 page 44
b1 b0
Symbol
CM0
Bit symbol
Clock output function
CM00
select bit
(Valid only in single-chip
CM01
mode)
WAIT peripheral function
CM02
clock stop bit
X -X
CIN COUT
CM03
select bit
CM04 Port X
C
Main clock stop bit
CM05
Main clock division select
CM06
bit 0
System clock select bit
CM07
elapses or the main clock oscillation stabilizes, whichever is longer.
d(M-L)
pin goes "H". Furthermore, because the internal feedback resistor
OUT
pin is pulled "H" to the same level as X
IN
-X
CIN COUT
Address After reset
0006 01001000
16
Bit name
b1 b0
0 0 : I/O port P5
0 1 : f output
C
1 0 : f output
8
1 1 : f
32
0 : Do not stop peripheral function
clock in wait mode
1 : Stop peripheral function clock
in wait mode (Note 2)
drive capacity
0 : LOW
(Note 3)
1 : HIGH
0 : I/O port P8
1 : X -X
select bit (Note 3)
CIN
0 : On
(Notes 5, 6, 7)
1 : Off (Notes 8, 9)
0 : CM16 and CM17 valid
(Notes 7, 10, 12) 1 : Division by 8 mode
0 : Main clock, PLL clock, or ring
oscillator clock
(Notes 6, 11)
1 : Sub clock
and P8
6
via the feedback resistor.
OUT
oscillator function), wait until the sub clock oscillates stably
Clock Generation Circuit
2
Function
7
output
, P8
6 7
generation function
COUT
(Note 4)
are directed for input, with no
7
RW
RW
RW
RW
RW
RW
RW
RW
RW