Renesas M16C/60 Series Hardware Manual page 168

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M16C/6N5 Group
(b) Serial Data Logic Switching Function
The data written to the UiTB register has its logic reversed before being transmitted. Similarly, the
received data has its logic reversed when read from the UiRB register. Figure 1.15.18 shows serial
data logic.
(1) When the UiC1 register's UiLCH bit = 0 (no reverse)
Transfer clock
(2) When the UiC1 register's UiLCH bit = 1 (reverse)
Transfer clock
i = 0 to 2
ST: Start bit
P: Parity bit
SP: Stop bit
Note: This applies to the case where the UiC0 register s CKPOL bit = 0 (transmit data
Figure 1.15.18 Serial Data Logic Switching
(c) TxD and RxD I/O Polarity Inverse Function
This function inverses the polarities of the TxD
input/output data (including the start, stop and parity bits) are inversed. Figure 1.15.19 shows the TxD
and RxD input/output polarity inverse.
(1) When the UiMR register's IOPOL bit = 0 (no reverse)
(2) When the UiMR register's IOPOL bit = 1 (reverse)
Transfer clock
i = 0 to 2
ST: Start bit
P: Parity bit
SP: Stop bit
Note: This applies to the case where the UiC0 register's UFORM bit = 0 (LSB first),
Figure 1.15.19 T D and R
X
Rev.1.00 2003.05.30 page 154
"H"
"L"
"H"
TxD
i
ST D0
(no reverse)
"L"
"H"
"L"
"H"
TxD
i
ST D0
(reverse)
"L"
output at the falling edge of the transfer clock), the UiC0 register's UFORM bit
= 0 (LSB first), the UiMR register's STPS bit = 0 (1 stop bit) and UiMR register's
PRYE bit = 1 (parity enabled).
"H"
Transfer clock
"L"
TxD
i "H"
ST D0
(no reverse)
"L"
RxD
ST D0
i "H"
(no reverse)
"L"
"H"
"L"
TxD
"H"
i
ST D0
(reverse)
"L"
"H"
RxD
ST D0
i
"L"
(reverse)
the UiMR register's STPS bit = 0 (1 stop bit) and the UiMR register's PRYE
bit = 1 (parity enabled).
D I/O Polarity Inverse
X
D1 D2 D3 D4 D5 D6
D1 D2 D3 D4 D5 D6
pin output and RxD
i
D1 D2 D3 D4 D5 D6
D1 D2 D3 D4 D5 D6
D1 D2 D3 D4 D5 D6
D1 D2 D3 D4 D5 D6
Serial I/O (UART Mode)
D7 P SP
D7 P SP
pin input. The logic levels of all
i
D7 P SP
D7 P SP
D7 P SP
D7 P SP