Timer B - Renesas M16C/60 Series Hardware Manual

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M16C/6N5 Group

Timer B

Figure 1.13.15 shows a block diagram of the timer B. Figures 1.13.16 and 1.13.17 show the timer B-related
registers.
Timer B supports the following three modes. Use the TMOD1 and TMOD0 bits of TBiMR register (i = 0 to 5)
to select the desired mode.
• Timer mode: The timer counts an internal count source.
• Event counter mode: The timer counts pulses from an external device or overflows or underflows of
• Pulse period/pulse width measuring mode: The timer measures an external signal's pulse period or
Clock source selection
f or f
1 2
f
8
f
32
f
C32
Polarity switching
TBi
IN
and edge pulse
Can be selected in only
event counter mode
TBj overflow (Note)
i = 0 to 5
j = i — 1. Note, however, j = 2 when i = 0, j = 5 when i = 3
Note: Overflow or underflow
Figure 1.13.15 Timer B Block Diagram
Rev.1.00 2003.05.30 page 114
other timers.
pulse width.
Timer mode
Pulse period measurement mode,
pulse width measurement mode
Clock selection
Event counter mode
Data bus high-order bits
Data bus low-order bits
Low-order 8 bits
Reload register
Counter
TABSR register
TBSR register
Counter reset circuit
TBi Addresses
Timer B0 0391 -0390
16
Timer B1 0393 -0392
16
Timer B2 0395 -0394
16
Timer B3 01D1 -01D0
16
Timer B4 01D3 -01D2
16
Timer B5 01D5 -01D4
16
Timer B
High-order 8 bits
TBj
Timer B2
16
Timer B0
16
Timer B1
16
Timer B5
16
Timer B3
16
Timer B4
16