Renesas M16C/60 Series Hardware Manual page 197

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M16C/6N5 Group
f
AD
AD
TRG
V
REF
VCUT=0
AV
SS
VCUT=1
PM00
PM01
(Note)
Port P0 group
AN
00
AN
01
AN
02
AN
03
AN
04
AN
05
AN
06
AN
07
Port P2 group
AN
20
AN
21
AN
22
AN
23
AN
24
AN
25
AN
26
AN
27
OPA0=1
ANEX
0
OPA1=1
ANEX
1
Note: Port P0 group (AN
to PM00 bits are set to "01
set to "11
2
Figure 1.16.1 A-D Converter Block Diagram
Rev.1.00 2003.05.30 page 183
A-D conversion rate selection
CKS2=0
1/2
1/3
CKS2=1
TRG=0
Software trigger
TRG=1
Resistor ladder
Successive conversion register
AD register 0 (16)
AD register 1 (16)
AD register 2 (16)
AD register 3 (16)
AD register 4 (16)
AD register 5 (16)
AD register 6 (16)
AD register 7 (16)
Data bus high-order
Data bus low-order
Port P10 group
AN
0
AN
1
AN
2
CH2 to CH0
AN
3
=000
2
AN
4
=001
2
AN
5
=010
2
AN
6
=011
2
AN
7
=100
2
=101
2
=110
2
=111
2
CH2 to CH0
=000
2
=001
2
=010
2
=011
2
=100
2
=101
2
=110
2 (Note) PM01 to PM00=00
=111 ADGSEL1 to ADGSEL0=10
2
OPA1 to OPA0=11
PM01 to PM00=00
2
ADGSEL1 to ADGSEL0=11
2
OPA1 to OPA0=11
2
to AN ) can be used as analog input pins even when the PM01
00 07
" (memory expansion mode) and the PM05 to PM04 bits are
2
" (multiplexed bus allocated to the entire CS space)
CKS0=1
1/2
CKS0=0
A-D trigger
ADCON1 register
ADCON0 register
Decoder
for A-D register
ADCON2 register
Decoder
for channel
selection
CH2 to CH0
=000
2
ADGSEL1 to ADGSEL0=00
=001
2
OPA1 to OPA0=00
=010
2
=011
2
=100
2
=101
2
PM01 to PM00=00
=110
2
ADGSEL1 to ADGSEL0=10
=111
2
OPA1 to OPA0=00
PM01 to PM00=00
ADGSEL1 to ADGSEL0=11
OPA1 to OPA0=00
ADGSEL1 to ADGSEL0=00
2
OPA1 to OPA0=11
2
2
2
2
OPA1 to OPA0
=01
2
OPA1=1
.
A-D Converter
CKS1=1
φ
AD
CKS1=0
V
REF
Comparator
V
IN
2
2
(Note)
2
2
2
2
2
2