Renesas M16C/60 Series Hardware Manual page 119

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M16C/6N5 Group
Timer Ai mode register (i = 0 to 4)
(When not using two-phase pulse signal processing)
b7 b6 b5 b4 b3 b2
0
Note 1: During event counter mode, the count source can be selected using the ONSF and TRGSR registers.
Note 2: Effective when the TAiTGH and TAiTGL bits of ONSF or TRGSR register are"00
Note 3: Count down when input on TAi
direction bit for TAi
Figure 1.13.8 TAiMR Register in Event Counter Mode (when not using two-phase pulse signal processing)
Rev.1.00 2003.05.30 page 105
b1 b0
Symbol
0 1
TA0MR to TA4MR
Bit symbol
TMOD0
Operation mode select bit
TMOD1
Pulse output function
MR0
select bit
Count polarity
MR1
select bit (Note 2)
Up/down switching
MR2
cause select bit
MR3
Set to "0" in event counter mode
Count operation type
TCK0
select bit
Can be "0" or "1" when not using two-phase pulse signal processing.
TCK1
pin is low or count up when input on that pin is high. The port
OUT
pin must be set to "0" (input mode).
OUT
Address After reset
0396 to 039A
16 16
Bit name
b1 b0
0 1 : Event counter mode (Note 1)
0 : Pulse is not output
(TA
iOUT
1 : Pulse is output
(TAi
OUT
0 : Counts external signal's falling edge
1 : Counts external signal's rising edge
0 : UDF register
1 : Input signal to TA
0 : Reload type
1 : Free-run type
00
16
Function
pin functions as I/O port)
pin functions as pulse output pin)
pin (Note 3)
iOUT
" (TAi pin input).
IN
2
Timer A
RW
R W
RW
RW
RW
RW
RW
RW
RW
RW