Renesas M16C/60 Series Hardware Manual page 175

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M16C/6N5 Group
• Detection of Start and Stop Condition
Whether a start or a stop condition has been detected is determined.
A start condition-detected interrupt request is generated when the SDAi pin changes state from high to
low while the SCLi pin is in the high state. A stop condition-detected interrupt request is generated
when the SDAi pin changes state from low to high while the SCLi pin is in the high state.
Figure 1.15.23 shows the detection of start and stop condition.
Because the start and stop condition-detected interrupts share the interrupt control register and vector,
check the UiSMR register's BBS bit to determine which interrupt source is requesting the interrupt.
3 to 6 cycles < duration for setting-up (Note)
3 to 6 cycles < duration for holding (Note)
(Start condition)
(Stop condition)
i = 0 to 2
Note: When the PCLKR register's PCLK1 bit = 1, this is the cycle number
Figure 1.15.23 Detection of Start and Stop Condition
• Output of Start and Stop Condition
A start condition is generated by setting the UiSMR4 register (i = 0 to 2)'s STAREQ bit to "1" (start).
A restart condition is generated by setting the UiSMR4 register's RSTAREQ bit to "1" (start).
A stop condition is generated by setting the UiSMR4 register's STPREQ bit to "1" (start).
The output procedure is described below.
(1) Set the STAREQ bit, RSTAREQ bit or STPREQ bit to "1" (start).
(2) Set the STSPSEL bit in the UiSMR4 register to "1" (output).
Table 1.15.12 and Figure 1.15.24 show the functions of the STSPSEL bit.
Rev.1.00 2003.05.30 page 161
SCLi
SDAi
SDA i
of f , and the PCLK1 bit = 0, this is the cycle number of f
1SIO
Duration for
Duration for
setting-up
holding
Serial I/O (Special Modes)
.
2SIO