Renesas M16C/60 Series Hardware Manual page 134

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M16C/6N5 Group
Timer Bi mode register (i = 0 to 5)
b7 b6 b5 b4 b3 b2 b1
1
Note: This flag is indeterminate after reset. When the TBiS bit = 1 (start counting), the MR3 bit is set to "0" (no overflow) by writing to the
TBiMR register at the next count timing or later after the MR3 bit was set to "1" (overflow). The MR3 bit cannot be set to "1" in a
program. The TB0S to TB2S bits are assigned to the TABSR register's bit 5 to bit 7, and the TB3S to TB5S bits are assigned to the
TBSR register's bit 5 to bit 7.
Figure 1.13.20 TBiMR Register in Pulse Period and Pulse Width Measurement Mode
Rev.1.00 2003.05.30 page 120
Symbol
b0
TB0MR to TB2MR 039B
0
TB3MR to TB5MR 01DB
Bit symbol Bit name
TMOD0
Operation mode
select bit
TMOD1
MR0
Measurement mode
select bit
MR1
TB0MR and TB3MR registers
Set to "0" in pulse period and pulse width measurement mode
MR2
TB1MR, TB2MR, TB4MR, TB5MR registers
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
Timer Bi overflow
MR3
flag ( Note)
TCK0
Count source
select bit
TCK1
Address After reset
to 039D 00XX0000
16 16 2
to 01DD 00XX0000
16 16 2
Function
b1 b0
1 0 : Pulse period / pulse width
measurement mode
b3 b2
0 0 : Pulse period measurement
(Measurement between a falling edge and the
next falling edge of measured pulse)
0 1 : Pulse period measurement
(Measurement between a rising edge and the next
rising edge of measured pulse)
1 0 : Pulse width measurement
(Measurement between a falling edge and the
next rising edge of measured pulse and between
a rising edge and the next falling edge)
1 1 : Must not be set.
0 : Timer did not overflow
1 : Timer has overflown
b7 b6
0 0 : f or f
1 2
0 1 : f
8
1 0 : f
32
1 1 : f
C32
Timer B
RW
RW
RW
RW
RW
RW
RO
RW
RW