Renesas M16C/60 Series Hardware Manual page 100

Under development
This document is under development and its contents are subject to change.
M16C/6N5 Group
Setting the PM22 bit to "1" results in the following conditions:
• The ring oscillator starts oscillating, and the ring oscillator clock becomes the watchdog timer count source.
Watchdog timer period =
• The CM10 bit of the CM1 register is disabled against write. (Writing a "1" has no effect, nor is stop mode entered.)
• The watchdog timer does not stop when in wait mode or hold state.
CPU
clock
HOLD
Write to WDTS register
RESET
Figure 1.11.1 Watchdog Timer Block Diagram
Watchdog timer control register
b7 b6 b5 b4 b3 b2
0 0
Watchdog timer start register (Note)
b7
Note: Write to the WDTS register after the watchdog timer interrupt occurs.
Figure 1.11.2 WDC Register and WDTS Register
Rev.1.00 2003.05.30 page 86
Watchdog timer count (32768)
ring oscillator clock
Prescaler
CM07 = 0
WDC7 = 0
1/16
CM07 = 0
WDC7 = 1
1/128
CM07 = 1
1/2
Ring oscillator clock
b1 b0
Symbol
WDC
Bit symbol
-
High-order bit of watchdog timer
(b4-b0)
-
Reserved bit
(b6-b5)
Prescaler select bit
WDC7
b0
Symbol
WDTS
The watchdog timer is initialized and starts counting after a write instruction to
this register. The watchdog timer value is always initialized to "7FFF
of whatever value is written.
PM22 = 0
Watchdog timer
PM22 = 1
Set to
"7FFF
Address After reset
000F 00XXXXXX
16
Bit name
Set to "0"
0 : Divided by 16
1 : Divided by 128
Address After reset
000E Indeterminate
16
Function
Watchdog Timer
PM12 = 0
Watchdog timer
interrupt request
PM12 = 1
Watchdog timer
Reset
"
16
2
Function
RW
RO
RW
RW
RW
WO
" regardless
16