Renesas M16C/60 Series Hardware Manual page 55

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M16C/6N5 Group
(1) Separate bus, 3-wait setting
BCLK
Write signal
Read signal
Data bus
Address bus
(2)Multiplexed bus, 1- or 2-wait setting
BCLK
Write signal
Read signal
Address bus
Address bus/
Data bus Address
(3)Multiplexed bus, 3-wait setting
BCLK
Write signal
Read signal
ALE
Address bus
Address bus/
Data bus
Note: These example timing charts indicate bus cycle length. After this bus cycle sometimes come read and
write cycles in succession.
Figure 1.7.8 Typical Bus Timings Using Software Wait (2)
Rev.1.00 2003.05.30 page 41
Bus cycle (Note)
Output
Address
CS
Bus cycle (Note)
ALE
Address
Data output
CS
Bus cycle (Note)
Address
Data output
Address
CS
Bus cycle (Note)
Address
Bus cycle (Note)
Address
Address
Input
Bus cycle (Note)
Address
Address
Bus Control
Input
Input