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M16C/6N5 Group
Table 1.22.5 Status Register
Status register
FMR0 register
bit
SR7 (D
)
FMR00
7
SR6 (D
)
-
6
SR5 (D
)
FMR07
5
SR4 (D
)
FMR06
4
SR3 (D
)
-
3
SR2 (D
)
-
2
SR1 (D
)
-
1
SR0 (D
)
-
0
Note: The FMR07 bit (SR5) and FMR06 bit (SR4) are set to "0" by executing the Clear Status Register command.
When the FMR07 bit (SR5) or FMR06 bit (SR4) = 1, the Program, Block Erase, Erase All Unlocked
Block, and Lock Bit Program commands are not accepted.
D
to D
: Indicates the data bus which is read out when the Read Status Register command is executed.
7
0
Rev.1.00
2003.05.30
page 276
Status name
bit
Sequencer status
Reserved
Erase status
Program status
Reserved
Reserved
Reserved
Reserved
Contents
"0"
"1"
Busy
Ready
-
-
Terminated normally
Terminated in error
Terminated normally
Terminated in error
-
-
-
-
-
-
-
-
Flash Memory
Value after reset
1
-
0
0
-
-
-
-
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