Renesas M16C/60 Series Hardware Manual page 59

Under development
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M16C/6N5 Group
System clock control register 1 (Note 1)
b7 b6 b5 b4 b3 b2
0 0 0
Note 1: Write to this register after setting the PRC0 bit of PRCR register to "1" (write enable)
Note 2: If the CM10 bit is "1" (stop mode), X
The X and X
CIN
or the CM20 bit of CM2 register is set to "1" (oscillation stop, re-oscillation detection function enabled), do
not set the CM10 bit to "1".
Note 3: When the PM22 bit of PM2 register is set to "1" (watchdog timer count source is ring oscillator clock), writing
to the CM10 bit has no effect.
Note 4: Effective when CM07 bit is "0" and CM21 bit is "0".
Note 5: After setting the PL07 bit in PLC0 register to "1" (PLL operation), wait until t
the CM11 bit to "1" (PLL clock).
Note 6: When entering stop mode from high- or middle-speed mode, or when the CM05 bit is set to "1" (main clock
turned off) in low-speed mode, the CM15 bit is set to "1" (drive capability high).
Note 7: Effective when the CM06 bit is "0" (CM16 and CM17 bits enabled).
Figure 1.8.3 CM1 Register
Rev.1.00 2003.05.30 page 45
b1 b0
Symbol
CM1
Bit symbol
All clock stop control bit
CM10
System clock select bit 1
CM11
-
Reserved bit
(b4-b2)
X -X
IN OUT
CM15
select bit
CM16
Main clock division
select bit 1
CM17
goes "H" and the internal feedback resistor is disconnected.
OUT
pins are placed in the high-impedance state. When the CM11 bit is set to "1" (PLL clock),
COUT
Address After reset
0007 00100000
16
Bit name
0 : Clock on
(Notes 2, 3) 1 : All clocks off (stop mode)
0 : Main clock
(Notes 3, 4) 1 : PLL clock (Note 5)
Set to "0"
drive capacity 0 : LOW
(Note 6) 1 : HIGH
b7 b6
0 0 : No division mode
0 1 : Division by 2 mode
(Note 7)
1 0 : Division by 4 mode
1 1 : Division by 16 mode
Clock Generation Circuit
2
Function
RW
RW
RW
RW
RW
RW
RW
(PLL) elapses before setting
su