Renesas M16C/60 Series Hardware Manual page 333

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M16C/6N5 Group
f
CAN
CPU read signal
Updating period of
CAN module
CPU reset signal
C0STR register
b8: State_Reset bit
0: CAN operation
mode
1: CAN reset/initial-
ization mode
Figure 1.11.1 When Updating Period of CAN Module Matches Access Period from CPU
CPU read signal
Updating period of
the CAN module
CPU reset signal
C0STR register
b8: State_Reset bit
0: CAN operation
mode
1: CAN reset/initial-
ization mode
Figure 1.11.2 With a Wait Time of 3f
CPU read signal
Updating period of
the CAN module
CPU reset signal
C0STR register
b8: State_Reset bit
0: CAN operation
mode
1: CAN reset/initial-
ization mode
Figure 1.11.3 When Polling Period of CPU is 3f
Rev.1.00 2003.05.30 page 19
✕ ✕
✕: When the CAN module's State_Reset bit updating period matches the CPU's read
period, it does not enter reset mode, for the CPU read has the higher priority.
Wait time
: Updated without fail in period of 3f
Before CPU Read
CAN
4f
CAN
✕
✕: When the CAN module's State_Reset bit updating period matches the CPU's read
period, it does not enter reset mode, for the CPU read has the higher priority.
: Updated without fail in period of 4f
CAN
1.11 Precautions for CAN Module
✕ ✕
CAN
CAN
or Longer
✕