Renesas M16C/60 Series Hardware Manual page 261

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M16C/6N5 Group
Switching Characteristics
(Referenced to V = 5 V, V
CC
Table 1.21.21 Memory Expansion Mode and Microprocessor Mode (for setting with no wait)
Symbol
t
Address output delay time
d(BCLK-AD)
t
Address output hold time (refers to BCLK)
h(BCLK-AD)
t
Address output hold time (refers to RD)
h(RD-AD)
t
Address output hold time (refers to WR)
h(WR-AD)
t
Chip select output delay time
d(BCLK-CS)
t
Chip select output hold time (refers to BCLK)
h(BCLK-CS)
t
ALE signal output delay time
d(BCLK-ALE)
t
ALE signal output hold time
h(BCLK-ALE)
t
RD signal output delay time
d(BCLK-RD)
t
RD signal output hold time
h(BCLK-RD)
t
WR signal output delay time
d(BCLK-WR)
t
WR signal output hold time
h(BCLK-WR)
t
Data output delay time (refers to BCLK)
d(BCLK-DB)
t
Data output hold time (refers to BCLK) (Note 3)
h(BCLK-DB)
t
Data output delay time (refers to WR)
d(DB-WR)
t
Data output hold time (refers to WR) (Note 3)
h(WR-DB)
Note 1: Calculated according to the BCLK frequency as follows:
0.5 ✕ 10 9
– 10 [ns]
f(BCLK)
Note 2: Calculated according to the BCLK frequency as follows:
0.5 ✕ 10
9
– 40 [ns]
f(BCLK)
Note 3: This standard value shows the timing when the output is off, and does not show hold time of data bus.
Hold time of data bus varies with capacitor volume and pull-up (pull-down) resistance value.
Hold time of data bus is expressed in
t = – CR ✕ ln (1 – V
by a circuit of the right figure.
For example, when V
R =1 kΩ, hold time of output "L" level is
t = – 30 pF ✕ 1 kΩ ✕ ln (1 – 0.2 V
Rev.1.00 2003.05.30 page 247
= 0 V, at Topr = –40 to 85 °C unless otherwise specified)
SS
Parameter
f(BCLK) is 12.5 MHz or less.
/ V )
OL CC
= 0.2 V , C = 30 pF,
OL CC
/ V ) = 6.7 ns.
CC CC
Measuring
condition
Figure 1.21.1
DBi
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
Figure 1.21.1. Port P0 to P10 Measurement Circuit
Electrical Characteristics
Standard
Unit
Min. Max.
25 ns
4 ns
ns
0
ns
(Note 1)
ns
25
ns
4
ns
25
ns
–4
ns
25
ns
0
ns
25
ns
0
ns
40
ns
4
ns
(Note 2)
ns
(Note 1)
R
C
30pF