Renesas M16C/60 Series Hardware Manual page 179

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M16C/6N5 Group
Special Mode 2
Multiple slaves can be serially communicated from one master. Transfer clock polarity and phase are
selectable. Table 1.15.13 lists the specifications of Special Mode 2. Figure 1.15.25 shows communication
control example for Special Mode 2. Table 1.15.14 lists the registers used in Special Mode 2 and the
register values set.
Table 1.15.13 Special Mode 2 Specifications
Item
Transfer data format
Transfer clock
Transmit/receive control
Transmission start condition
Reception start condition
Interrupt request
generation timing
Error detection
Select function
i = 0 to 2
Note 1: When an external clock is selected, the conditions must be met while if the UiC0 register's CKPOL bit = 0
(transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the
external clock is in the high state; if the UiC0 register's CKPOL bit = 1 (transmit data output at the rising edge and
the receive data taken in at the falling edge of the transfer clock), the external clock is in the low state.
Note 2: The U0IRS and U1IRS bits respectively are the UCON register bits 0 and 1; the U2IRS bit is the U2C1 register bit 4.
Note 3: If an overrun error occurs, the value of UiRB register will be indeterminate. The IR bit of SiRIC register does not
change.
Rev.1.00 2003.05.30 page 165
• Transfer data length: 8 bits
• Master mode
UiMR register's CKDIR bit = 0 (internal clock) : fj/ 2(n+1)
fj = f , f , f , f . n: Setting value of UiBRG register
1SIO 2SIO 8SIO 32SIO
• Slave mode
CKDIR bit = 1 (external clock selected) : Input from CLKi pin
Controlled by input/output ports
• Before transmission can start, the following requirements must be met (Note 1)
_
The TE bit of UiC1 register = 1 (transmission enabled)
_
The TI bit of UiC1 register = 0 (data present in UiTB register)
• Before reception can start, the following requirements must be met (Note 1)
_
The RE bit of UiC1 register = 1 (reception enabled)
_
The TE bit of UiC1 register = 1 (transmission enabled)
_
The TI bit of UiC1 register = 0 (data present in the UiTB register)
• For transmission, one of the following conditions can be selected
_
The UiIRS bit (Note 2) = 0 (transmit buffer empty): when transferring data from the
UiTB register to the UARTi transmit register (at start of transmission)
_
The UiIRS bit =1 (transfer completed): when the serial I/O finished sending data from
the UARTi transmit register
• For reception
When transferring data from the UARTi receive register to the UiRB register (at
completion of reception)
• Overrun error (Note 3)
This error occurs if the serial I/O started receiving the next data before reading the
UiRB register and received the 7th bit of the next data
• Clock phase setting
Selectable from four combinations of transfer clock polarities and phases
Serial I/O (Special Modes)
Specification
00
16
to FF
16