Renesas M16C/60 Series Hardware Manual page 255

Under development
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M16C/6N5 Group
Table 1.21.2 Recommended Operating Conditions (Note 1)
Symbol
Supply voltage (V
V , V
CC1 CC2
AV Analog supply voltage
CC
V Supply voltage
SS
AV Analog supply voltage
SS
V HIGH input
IH
voltage
V
LOW input
IL
voltage
I
HIGH peak output
OH (peak)
current
I
HIGH average
OH (avg)
output current
I
LOW peak output
OL (peak)
current
I
LOW average
OL (avg)
output current
f(X ) Main clock input
IN
oscillation frequency
(Notes 4, 5 and 6)
f(X ) Sub clock oscillation frequency
CIN
f(Ring) Ring oscillation frequency
f(PLL) PLL clock oscillation frequency
f(BCLK) CPU operation clock
PLL frequency synthesizer stabilization wait time
t (PLL)
su
Note 1: Referenced to V
Note 2: The mean output current is the mean value within 100 ms.
Note 3: The total I (peak) for ports P0, P1, P2, P8
OL
P9 and P10 must be 80mA max. The total I
(peak) for ports P3, P4, P5, P6, P7 and P8
must be 80mA max. The total I
P0, P1, and P2 must be –40mA max. The total I
(peak) for ports P3, P4 and P5 must be –40mA
max. The total I
to P8 must be –40mA max. The total I
4
for ports P8 , P8
6 7
Note 4: Relationship between main clock oscillation
frequency and supply voltage is shown right.
Note 5: Execute program /erase of flash memory by
V = 5.0 ± 0.5 V.
CC
Note 6: When using 16 MHz or more, use PLL clock.
Rev.1.00 2003.05.30 page 241
Parameter
=V )
CC1 CC2
P3 ~P3 , P4 ~P4 , P5
1 7 0 7 0
P7 , P7 ~P7 , P8 ~P8
0 2 7 0 7
____________
X , RESET, CNV , BYTE
IN SS
P7 , P9
1 1
P0 ~P0 , P1 ~P1 , P2
0 7 0 7 0
P0 ~P0 , P1 ~P1 , P2
0 7 0 7 0
(Data input during memory expansion and microprocessor modes)
P3 ~P3 , P4 ~P4 , P5
1 7 0 7 0
P7 ~P7 , P8 ~P8 , P9
0 7 0 7 0
____________
X , RESET, CNV , BYTE
IN SS
P0 ~P0 , P1 ~P1 , P2
0 7 0 7 0
P0 ~P0 , P1 ~P1 , P2
0 7 0 7 0
(Data input during memory expansion and microprocessor modes)
P0 ~P0 , P1 ~P1
0 7 0
P4 ~P4 , P5 ~P5
0 7 0
P8 ~P8 , P8 , P8
0 4 6
P0 ~P0 , P1 ~P1
0 7 0
P4 ~P4 , P5 ~P5
0 7 0
P8 ~P8 , P8 , P8
0 4 6
P0 ~P0 , P1 ~P1
0 7 0
P4 ~P4 , P5 ~P5
0 7 0
P8 ~P8 , P8 , P8
0 4 6
P0 ~P0 , P1 ~P1
0 7 0
P4 ~P4 , P5 ~P5
0 7 0
P8 ~P8 , P8 , P8
0 4 6
No wait Mask ROM version V
Flash memory version
= 4.2 to 5.5 V at Topr = –40 to 85 °C unless otherwise specified.
CC
0
(peak) for ports
OH
(peak) for ports P6, P7 and P8
OH
OH
, P9 and P10 must be –40mA max.
~P5 , P6 ~P6 ,
7 0 7
, P9 , P9 ~P9 , P10 ~P10 ,
0 2 7 0 7
~P2 , P3 (During single-chip mode)
7 0
~P2 , P3
7 0
~P5 , P6 ~P6 ,
7 0 7
~P9 , P10 ~P10 ,
7 0 7
~P2 , P3 (During single-chip mode)
7 0
~P2 , P3
7 0
, P2 ~P2 , P3 ~P3 ,
7 0 7 0 7
, P6 ~P6 , P7 , P7 ~P7 ,
7 0 7 0 2 7
, P9 , P9 ~P9 , P10 ~P10
7 0 2 7 0
, P2 ~P2 , P3 ~P3 ,
7 0 7 0 7
, P6 ~P6 , P7 , P7 ~P7 ,
7 0 7 0 2 7
, P9 , P9 ~P9 , P10 ~P10
7 0 2 7 0
, P2 ~P2 , P3 ~P3 ,
7 0 7 0 7
, P6 ~P6 , P7 ~P7 ,
7 0 7 0 7
, P9 ~P9 , P10 ~P10
7 0 7 0 7
, P2 ~P2 , P3 ~P3 ,
7 0 7 0 7
, P6 ~P6 , P7 ~P7 ,
7 0 7 0 7
, P9 ~P9 , P10 ~P10
7 0 7 0 7
=4.2 to 5.5V
CC
V =4.2 to 5.5V
CC
, P8 ,
6 7
Main clock input oscillation frequency
OL
(Mask ROM, flash memory version: no wait)
to P8
4
16.0
OH
0
(peak)
0.0
Electrical Characteristics
Standard
Min. Typ. Max.
4.2 5.0
V
CC
0
0
0.8V V
CC
0.8V
CC
0.8V V
CC
0.5V V
CC
0 0.2V
0 0.2V
0 0.16V
–10.0
7
–5.0
7
10.0
0
32.768
1
0
4.2 5.5
V [V] (main clock: no division)
CC
Unit
5.5 V
V
V
V
V
CC
6.5 V
V
CC
V
CC
V
CC
V
CC
V
CC
mA
mA
mA
mA
5.0
MHz
16
50 kHz
MHz
MHz
20
20 MHz
20 ms