Renesas M16C/60 Series Hardware Manual page 275

Under development
This document is under development and its contents are subject to change.
M16C/6N5 Group
ROM code protect control address
b7 b6 b5 b4 b3 b2
1 1 1 1
Note 1: Once any of these bits is set to "0", it cannot be set back to "1". If a memory block that contains the
ROMCP register is erased, the ROMCP register is set to "FF
Note 2: If the ROMCR bits are set to "00
bits cannot be modified during parallel I/O mode, they need to be modified in standard serial I/O or other
modes.
Note 3: If the ROMCR bits are set to other than "00
code protect enabled), the flash memory is disabled against reading and rewriting in parallel input/output
mode.
Note 4: The ROMCP1 bits are effective when the ROMCR bits are "01
Figure 1.22.2 ROMCP Register
0FFFDF
0FFFE3
0FFFE7
0FFFEB
0FFFEF
0FFFF3
0FFFF7
0FFFFB
0FFFFF
Figure 1.22.3 Address for ID Code Stored
Rev.1.00 2003.05.30 page 261
b1 b0
Symbol
ROMCP
Bit symbol
-
Reserved bit
(b3-b0)
ROM code protect
ROMCR
reset bit
ROM code protect level
ROMCP1
1 set bit
", ROM code protect level 1 is removed. However, because the ROMCR
2
Address
to 0FFFDC Undefined instruction vector
ID1
16 16
to 0FFFE0 Overflow vector
ID2
16 16
to 0FFFE4 BRK instruction vector
16 16
Address match vector
to 0FFFE8 ID3
16 16
Single step vector
to 0FFFEC ID4
16 16
Oscillation stop and re-oscillation detection/Watchdog timer vector
to 0FFFF0 ID5
16 16
to 0FFFF4 ID6 DBC vector
16 16
ID7 NMI vector
to 0FFFF8
16 16
Reset vector
ROMCP
to 0FFFFC
16 16
Address Value when shipped
0FFFFF FF (Note 1)
16 16
Bit name
Set to "1"
b5 b4
0 0 : Removes protect
0 1 :
(Notes 1, 2)
1 0 :
1 1 :
b7 b6
0 0 :
0 1 :
(Notes 1, 3, 4)
1 0 :
1 1 : Protect disabled
".
16
" and the ROMCP1 bits are set to other than "11
2
", "10 " or "11
2 2
4 bytes
Flash Memory
Function
RW
RW
RW
Enables ROOMCP1 bit
RW
RW
Protect enabled
RW
" (ROM
2
".
2