Renesas M16C/60 Series Hardware Manual page 171

Under development
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M16C/6N5 Group
SDAi
Noise
Filter
SCLi
Noise
Filter
This diagram applies to the case where the UiMR register's SMD2 to SMD0 bits = 010
i = 0 to 2
IICM: UiSMR register's bit
IICM2, SWC, ALS, SWC2, SDHI: UiSMR2 register's bits
STSPSEL, ACKD, ACKC: UiSMR4 register's bits
Note: If the IICM bit =1, the pins can be read even when the PD6_2, PD6_6 or PD7_1 bit = 1 (output mode).
2
Figure 1.15.21 I C Mode Block Diagram
Rev.1.00 2003.05.30 page 157
STSPSEL=1
Delay
circuit
STSPSEL=0
ACKC=1 ACKC=0
SDHI
ALS
ACKD bit
D Arbitration
Q
T
Start condition
detection
Stop condition
detection
Falling edge
detection
Port register
IICM=0 R
(Note)
I/O port
Q
Internal clock
STSPSEL=0
UARTi
IICM=1
STSPSEL=1 External
clock
Start and stop condition generation block
SDA
STSP
SCL
STSP
IICM2=1
Transmission
register
UARTi
Reception register
UARTi
S
Bus
Q
R busy
D
Q
T
D
Q
ACK
T
9th bit
SWC2
CLK
control
UARTi
9th bit falling edge
R
S SWC
and the UiSMR register's IICM bit = 1.
2
Serial I/O (Special Modes)
DMA0, DMA1 request
(UART1: DMA0 only)
UARTi transmit,
NACK interrupt
request
IICM=1 and
IICM2=0
DMA0
(UART0, UART2)
IICM2=1
UARTi receive,
ACK interrupt request,
DMA1 request
IICM=1 and
IICM2=0
NACK
Start/stop condition
detection
interrupt request