Renesas M16C/60 Series Hardware Manual page 54

Under development
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M16C/6N5 Group
(1) Separate bus, No wait setting
(2) Separate bus, 1-wait setting
(3) Separate bus, 2-wait setting
Note: These example timing charts indicate bus cycle length. After this bus cycle sometimes come read and
write cycles in succession.
Figure 1.7.7 Typical Bus Timings Using Software Wait (1)
Rev.1.00 2003.05.30 page 40
Bus cycle (Note)
BCLK
Write signal
Read signal
Data bus
Address bus
Address
CS
Bus cycle (Note)
BCLK
Write signal
Read signal
Data bus
Address bus Address
CS
Bus cycle (Note)
BCLK
Write signal
Read signal
Data bus
Address bus
CS
Bus cycle (Note)
Output Input
Address
Bus cycle (Note)
Output
Address
Output
Address
Bus Control
Input
Bus cycle (Note)
Input
Address