Special Mode 2 - Renesas M16C/60 Series Hardware Manual

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M16C/6N5 Group
Special Mode 1 (I
2
I C mode is provided for use as a simplified I
specifications of the I
the registers used in the I
mode. Figure 1.15.22 shows SCLi timing.
As shown in Table 1.15.11, the microcomputer is placed in I
"010 " and the IICM bit to "1". Because SDAi transmit output has a delay circuit attached, SDAi output
2
does not change state until SCLi goes low and remains stably low.
2
Table 1.15.9 I C Mode Specifications
Item
Transfer data format
Transfer clock
Transmission start condition
Reception start condition
Interrupt request
generation timing
Error detection
Select function
i = 0 to 2
Note 1: When an external clock is selected, the conditions must be met while the external clock is in the high
state.
Note 2: If an overrun error occurs, the value of UiRB register will be indeterminate. The IR bit of SiRIC
register does not change.
Rev.1.00 2003.05.30 page 156
2
C Mode)
2
C mode. Figure 1.15.21 shows the block diagram for I
2
C mode and the register values set. Table 1.15.11 lists the features in I
• Transfer data length: 8 bits
• During master
UiMR register's CKDIR bit = 0 (internal clock) : fj/ 2(n+1)
fj = f , f , f , f
1SIO 2SIO 8SIO 32SIO
• During slave
CKDIR bit = 1 (external clock ) : Input from SCL
• Before transmission can start, the following requirements must be met (Note 1)
_
The TE bit of UiC1 register = 1 (transmission enabled)
_
The TI bit of UiC1 register = 0 (data present in UiTB register)
• Before reception can start, the following requirements must be met (Note 1)
_
The RE bit of UiC1 register = 1 (reception enabled)
_
The TE bit of UiC1 register = 1 (transmission enabled)
_
The TI bit of UiC1 register = 0 (data present in the UiTB register)
When start or stop condition is detected, acknowledge undetected, and acknowledge
detected
• Overrun error (Note 2)
This error occurs if the serial I/O started receiving the next data before reading the
UiRB register and received the 8th bit of the next data
• Arbitration lost
Timing at which the UiRB register's ABT bit is updated can be selected
• SDAi digital delay
No digital delay or a delay of 2 to 8 UiBRG count source clock cycles selectable
• Clock phase setting
With or without clock delay selectable
2
C interface compatible mode. Table 1.15.9 lists the
2
C mode by setting the SMD2 to SMD0 bits to
Specification
. n: Setting value of UiBRG register
pin
i
Serial I/O (Special Modes)
2
C mode. Table 1.15.10 lists
00 to FF
16 16
2
C