Renesas M16C/60 Series Hardware Manual page 76

Under development
This document is under development and its contents are subject to change.
M16C/6N5 Group
Main clock oscillation
PLL operation mode
CPU clock: f(PLL)
CM07=0
CM06=0
CM17=0
CM16=0
CM04=1 CM04=0
PLL operation
mode
CPU clock: f(PLL)
CM07=0
CM06=0
CM17=0
CM16=0
Sub clock oscillation
CM04, CM05, CM06, CM07 : CM0 register's bits
CM11, CM15, CM16, CM17 : CM1 register's bits
CM20, CM21 : CM2 register's bits
PLC07 : PLC0 register's bit
Note 1: Avoid making a transition when the CM20 bit is set to "1" (oscillation stop, re-oscillation detection function enabled). Set the CM20 bit to "0" (oscillation stop, re-oscillation detection function disabled)
before transiting.
Note 2: Wait for t or the main clock oscillation stabilization time whichever is longer before switching over.
d(M-L)
Note 3: Switch clock after oscillation of sub clock is sufficiently stable.
Note 4: Change CM17 and CM16 before changing CM06.
Note 5: Transit in accordance with arrow.
Note 6: PLL operation mode can only be entered from high speed mode. Also, wait until the PLL clock is sufficiently stable before changing operation modes. To select a 16 MHz or higher PLL clock, set the
PM20 bit to "0" (SFR accessed with two wait states) before setting PLC07 to "1" (PLL operation).
Note 7: PLL operation mode can only be changed to high speed mode. If the PM20 bit = 0 (SFR accessed with two wait states), set PLC07 to "0" (PLL turned off) before setting the PM20 bit to "1" (SFR
accessed with one wait state).
Note 8: Set the CM06 bit to "1" (division by 8 mode) before changing back the operation mode from ring oscillator mode to high- or middle-speed mode.
Note 9: When the CM21 bit = 0 (ring oscillator turned off) and the CM05 bit = 1 (main clock turned off), the CM06 bit is fixed to "1" (divide-by-8 mode) and the CM15 bit is fixed to "1" (drive capability High).
Figure 1.8.13 State Transition in Normal Operation Mode
Rev.1.00 2003.05.30 page 62
Middle-speed mode
Middle-speed mode
PLC07=1
High-speed mode (divide by 4)
(divide by 2)
CM11=1
(Note 6) CPU clock: f(X ) CPU clock: f(X )/2
IN IN CPU clock: f(X
CM07=0 CM07=0
CM06=0 CM06=0
CM17=0 CM17=0
PLC07=0
CM11=0
CM16=0 CM16=1
(Note 7)
CM04=1
Middle-speed mode
Middle-speed mode
PLC07=1 High-speed mode (divide by 4)
(divide by 2)
CM11=1
(Note 6)
CPU clock: f(X ) CPU clock: f(X )/2 CPU clock: f(X
IN IN
CM07=0 CM07=0
CM06=0 CM06=0
PLC07=0
CM17=0 CM17=0
CM11=0
CM16=0 CM16=1
(Note 7)
CM07=1
(Note 3)
Low-speed mode
CPU clock: f(X
CM05=1
(Notes 1, 9)
Low power dissipation mode
CPU clock: f(X
Middle-speed mode Middle-speed mode
(divide by 8) (divide by 16)
CM21=0
)/4
IN CPU clock: f(X )/8 CPU clock: f(X )/16
IN IN
CM07=0 CM07=0
CM07=0
CM06=0 CM06=0
CM17=1 CM17=1
CM06=1 CM21=1
CM16=0 CM16=1
CM04=0
Middle-speed mode Middle-speed mode
(divide by 8) (divide by 16)
CM21=0
)/4 CPU clock: f(X )/8 CPU clock: f(X )/16
IN IN IN (Note 8)
CM07=0 CM07=0
CM07=0
CM06=0 CM06=0
CM17=1 CM17=1
CM06=1 CM21=1
CM16=0 CM16=1
CM07=0
(Notes 2, 4)
CM21=0
)
CIN
CM07=1
CM21=1
CM05=0
)
CIN
CM07=1
CM06=1
CM15=1
Clock Generation Circuit
Ring oscillator clock
oscillation
Ring oscillator low power
Ring oscillator mode
dissipation mode
CPU clock CPU clock
CM05=0
(Note 8)
f(Ring) f(Ring)
f(Ring)/2 f(Ring)/2
f(Ring)/4 f(Ring)/4
f(Ring)/8 f(Ring)/8
CM05=1
f(Ring)/16 f(Ring)/16
(Note 1)
CM04=1 CM04=0 CM04=1
Ring oscillator
Ring oscillator low power
mode dissipation mode
CPU clock CPU clock
CM05=0
f(Ring) f(Ring)
f(Ring)/2 f(Ring)/2
f(Ring)/4 f(Ring)/4
f(Ring)/8 f(Ring)/8
f(Ring)/16 f(Ring)/16
CM05=1
(Note 1)
Low-speed mode
CPU clock: f(X CIN )
CM07=1
CM04=0