Renesas M16C/60 Series Hardware Manual page 151

Under development
This document is under development and its contents are subject to change.
M16C/6N5 Group
UARTi transmit/receive mode register (i = 0 to 2)
b7 b6 b5 b4 b3 b2 b1
Note 1: To receive data, set the corresponding port direction bit for each RxDi pin to "0" (input mode).
Note 2: Set the corresponding port direction bit for SCL and SDA pins to "0" (input mode).
Note 3: Set the corresponding port direction bit for each CLKi pin to "0" (input mode).
UARTi transmit/receive control register 0 (i = 0 to 2)
b7 b6 b5 b4 b3 b2 b1
Note 1: CTS /RTS can be used when the UCON register's CLKMD1 bit = 0 (only CLK1 output) and the UCON register's RCSP bit = 0
1 1
(CTS /RTS not separated).
0 0
Note 2: Set the corresponding port direction bit for each CTSi pin to "0" (input mode).
Note 3: SCL /P7 is N channel open-drain output. Cannot be set to the CMOS output. Set the NCH bit of the U2C0 register to "0".
2 1
Note 4: Effective for clock synchronous serial I/O mode and UART mode transfer data 8-bit long.
Figure 1.15.4 U0MR to U2MR Registers and U0C0 to U2C0 Registers
Rev.1.00 2003.05.30 page 137
b0
Symbol
U0MR to U2MR 03A0
16
Bit
Bit name
symbol
Serial I/O mode select bit
SMD0
(Note 1)
SMD1
SMD2
Internal/external clock
CKDIR
select bit
STPS Stop bit length select bit
PRY
Odd/even parity select bit
PRYE
Parity enable bit
TxD, RxD I/O polarity
IOPOL
reverse bit
b0
Symbol
U0C0 to U2C0 03A4
16
Bit
Bit name
symbol
CLK0
BRG count source
select bit
CLK1
CTS/RTS function
CRS select bit
(Note 1)
Transmit register empty
TXEPT
flag
CRD CTS/RTS disable bit
Data output select bit
NCH
(Note 3)
CKPOL CLK polarity select bit
Transfer format select bit
UFORM
(Note 4)
Address After reset
, 03A8 , 01F8 00
16 16 16
b2 b1 b0
0 0 0 : Serial I/O disabled
0 0 1 : Clock synchronous serial I/O mode
2
0 1 0 : I C mode
1 0 0 : UART mode transfer data 7-bit long
1 0 1 : UART mode transfer data 8-bit long
1 1 0 : UART mode transfer data 9-bit long
Must not be set except above
0 : Internal clock
1 : External clock (Note 3)
0 : One stop bit
1 : Two stop bits
Effective when PRYE = 1
0 : Odd parity
1 : Even parity
0 : Parity disabled
1 : Parity enabled
0 : No reverse
1 : Reverse
Address After reset
, 03AC , 01FC 00001000
16 16 2
b1 b0
0 0 : f or f is selected
1SIO 2SIO
0 1 : f is selected
8SIO
1 0 : f is selected
32SIO
1 1 : Must not be set
Effective when CRD = 0
0 : CTS function is selected (Note 2)
1 : RTS function is selected
0 : Data present in transmit register (during transmission)
1 : No data present in transmit register
(transmission completed)
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(P6 , P6 and P7 can be used as I/O ports)
0 4 3
0 : TxDi/SDAi and SCLi pins are CMOS output
1 : TxDi/SDAi and SCLi pins are N channel open-drain output
0 : Transmit data is output at falling edge of transfer clock
and receive data is input at rising edge
1 : Transmit data is output at rising edge of transfer clock
and receive data is input at falling edge
0 : LSB first
1 : MSB first
Function
(Note 2)
Function
Serial I/O
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
RW
RW
RW
RW