Renesas M16C/60 Series Hardware Manual page 181

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M16C/6N5 Group
Table 1.15.14 Registers to Be Used and Settings in Special Mode 2
Register Bit
UiTB (Note 1) 0 to 7
UiRB (Note 1) 0 to 7
OER
UiBRG 0 to 7
UiMR (Note 1) SMD2 to SMD0
CKDIR
IOPOL
UiC0 CLK1, CLK0
CRS
TXEPT
CRD
NCH
CKPOL
UFORM
UiC1 TE
TI
RE
RI
U2IRS (Note 2)
U2RRM (Note 2),
U2LCH, UiERE
UiSMR 0 to 7
UiSMR2 0 to 7
UiSMR3 CKPH
NODC
0, 2, 4 to 7
UiSMR4 0 to 7
UCON U0IRS, U1IRS
U0RRM, U1RRM
CLKMD0
CLKMD1, RCSP, 7 Set to "0"
i = 0 to 2
Note 1: Not all register bits are described above. Set those bits to "0" when writing to the registers in Special
Mode 2.
Note 2: Set the U0C1 and U1C1 register bit 4 and bit 5 to "0". The U0IRS, U1IRS, U0RRM and U1RRM bits
are in the UCON register.
Rev.1.00 2003.05.30 page 167
Set transmission data
Reception data can be read
Overrun error flag
Set a transfer rate
Set to "001 "
2
Set this bit to "0" for master mode or "1" for slave mode
Set to "0"
Select the count source for the UiBRG register
Invalid because CRD = 1
Transmit register empty flag
Set to "1"
Select TxDi pin output format
Clock phases can be set in combination with the UiSMR3 register's CKPH bit
Set to "0"
Set this bit to "1" to enable transmission
Transmit buffer empty flag
Set this bit to "1" to enable reception
Reception complete flag
Select UART2 transmit interrupt cause
Set to "0"
Set to "0"
Set to "0"
Clock phases can be set in combination with the UiC0 register's CKPOL bit
Set to "0"
Set to "0"
Set to "0"
Select UART0 and UART1 transmit interrupt cause
Set to "0"
Invalid because CLKMD1 = 0
Serial I/O (Special Modes)
Function