A-D Converter - Renesas M16C/60 Series Hardware Manual

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M16C/6N5 Group

A-D Converter

The microcomputer contains one A-D converter circuit based on 10-bit successive approximation method
configured with a capacitive-coupling amplifier. The analog inputs share the pins with P10
P9 , P0 to P0 , and P2
6 0 7
inputs, make sure the corresponding port direction bits are set to "0" (input mode).
When not using the A-D converter, set the VCUT bit to "0" (V
from the V pin into the resistor ladder, helping to reduce the power consumption of the chip.
REF
The A-D conversion result is stored in the ADi register bits for AN
Table 1.16.1 shows the performance of the A-D converter. Figure 1.16.1 shows the block diagram of the A-D
converter, and Figures 1.16.2 and 1.16.3 show the A-D converter-related registers.
Table 1.16.1 A-D Converter Performance
Item
Method of A-D conversion Successive approximation (capacitive coupling amplifier)
Analog input voltage (Note 1) 0V to AV
Operating clock φ
(Note 2) f
AD
Resolution
Integral nonlinearity error
Operating modes
Analog input pins
A-D conversion start condition • Software trigger
Conversion speed per pin • Without sample and hold function
Note 1: Does not depend on use of sample and hold function.
Note 2: Operation clock frequency (φ
A case without sample-and-hold function, turn (φ
A case with the sample and hold function, turn (φ
Rev.1.00 2003.05.30 page 182
_________
to P2 . Similarly, AD
0 7 TRG
(V )
CC CC
, divide-by-2 of f
AD AD
divide-by-12 of f
AD
8 bits or 10 bits (selectable)
• With 8-bit resolution: ±2LSB
• With 10-bit resolution : ±3LSB
When external operation amp connection mode is selected : ±7LSB
One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0,
and repeat sweep mode 1
8 pins (AN to AN ) + 2 pins (ANEX0 and ANEX1) + 8 pins (AN
0 7
+ 8 pins (AN to AN
20
The ADCON0 register's ADST bit is set to "1" (A-D conversion starts)
• External trigger (retriggerable)
__________
Input on the AD pin changes state from high to low after the ADST bit is set
TRG
to "1" (A-D conversion starts)
8-bit resolution: 49 φ
• With sample and hold function
8-bit resolution: 28 φ
frequency) must be 10 MHz or less.
AD
input shares the pin with P9
unconnected), so that no current will flow
REF
, AN , and AN
i 0i
Performance
, divide-by-3 of f , divide-by-4 of f
AD
)
27
cycles, 10-bit resolution: 59 φ
AD
cycles, 10-bit resolution: 33 φ
AD
frequency) into 250 kHz or more.
AD
frequency) into 1 MHz or more.
AD
A-D Converter
to P10
0 7
. Therefore, when using these
7
pins (i = 0 to 7).
2i
, divide-by-6 of f
AD
to AN
00 07
cycles
AD
cycles
AD
, P9 ,
5
,
AD
)