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This document is under development and its contents are subject to change.
M16C/6N5 Group
(a) SI/O3 Operation Timing
Figure 1.15.36 shows the SI/O3 operation timing.
"H"
SI/O3 internal clock
"L"
"H"
CLK
output
3
"L"
Signal written to the
"H"
S3TRR register
"L"
"H"
S
output
OUT3
"L"
"H"
S
input
IN3
"L"
"1"
S3IC register IR bit
"0"
* This diagram applies to the case where the S3C register bits are set as follows:
SM32 = 0 (S
OUT3
SM33 = 1 (S
OUT3
SM34 = 0 (transmit data output at the falling edge and receive data input at the rising edge of the transfer clock)
SM35 = 0 (LSB first)
SM36 = 1 (internal clock)
Note 1: If the SM36 bit = 1 (internal clock), the serial I/O starts sending or receiving data a maximum of 1.5 transfer clock cycles after writing to the
S3TRR register.
Note 2: When the SM36 bit = 1 (internal clock), the S
Figure 1.15.36 SI/O3 Operation Timing
(b) CLK Polarity Selection
The S3C register's SM34 bit allows selection of the polarity of the transfer clock. Figure 1.15.37 shows
the polarity of the transfer clock.
(1) When S3C register's SM34 bit = 0
CLK
3
S
IN3
S
OUT3
(2) When S3C register's SM34 bit = 1
CLK
3
S
IN3
S
OUT3
*This diagram applies to the case where the S3C register bits are set as follows:
Note 1: When the SM36 bit = 1 (internal clock), a high level is output from the CLK
transferring data.
Note 2: When the SM36 bit = 1 (internal clock), a low level is output from the CLK
transferring data.
Figure 1.15.37 Polarity of Transfer Clock
Rev.1.00
2003.05.30
page 180
1.5 cycle (max.)
(Note 1)
D
0
output)
output, CLK
function)
3
pin is placed in the high-impedance state after the transfer finishes.
OUT3
D0
D
D
1
D
D
D
0
1
D
D
D
0
1
D
D
D
0
1
SM35 = 0 (LSB first)
SM36 = 1 (internal clock)
D
D
D
D
1
2
3
4
D
D
D
D
2
3
4
5
6
D
D
D
D
2
3
4
5
6
D
D
D
D
2
3
4
5
6
D
D
D
D
2
3
4
5
6
(Note 2)
D
D
D
5
6
7
(Note 1)
D
7
D
7
(Note 2)
D
7
D
7
pin if not
3
pin if not
3
SI/O3
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