Renesas M16C/60 Series Hardware Manual page 87

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M16C/6N5 Group
Interrupt control register (Note 1)
b7 b6 b5 b4 b3 b2
0
Note 1: To rewrite the interrupt control registers, do so at a point that does not generate the interrupt request for that
register. For details, refer to "Precautions for Interrupts" of the Usage Notes Reference Book.
Note 2: When the BYTE pin is low and the processor mode is memory expansion or microprocessor mode, set the
ILVL2 to ILVL0 bits in the INT5IC to INT3IC registers to "000
Note 3: This bit can only be reset by writing "0" (Do not write "1").
Note 4: If the IFSR1 register's IFSR1i bit (i = 0 to 5) is "1" (both edges), set the INTiIC register's POL bit to "0" (falling edge).
Note 5: Set the S3IC register's POL bit to "0" (falling edge) when the IFSR0 register's IFSR00 bit = 1 and the IFSR1
register's IFSR16 bit = 0 (SI/O3 selected).
Figure 1.10.4 Interrupt Control Registers (2)
Rev.1.00 2003.05.30 page 73
Symbol
INT3IC (Note 2)
b1 b0
INT5IC
S3IC/INT4IC
INT0IC to INT2IC
Bit symbol
ILVL0
Interrupt priority level
ILVL1
select bit
ILVL2
Interrupt request bit
IR
Polarity select bit
POL
-
Reserved bit
(b5)
Nothing is assigned. When write, set to "0".
-
(b7-b6)
When read, their contents are indeterminate.
Address
0044
16
0048
16
0049
16
005D to 005F
16
Bit name
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
0 : Interrupt not requested
1 : Interrupt requested
0 : Selects falling edge (Notes 4, 5)
1 : Selects rising edge
Set to "0"
" (interrupt disabled).
2
After reset
XX00X000
2
XX00X000
2
XX00X000
2
XX00X000
16 2
Function
RW
RW
RW
RW
RW
(Note 3)
RW
RW
Interrupts
-