Renesas M16C/60 Series Hardware Manual page 270

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M16C/6N5 Group
Memory Expansion Mode and Microprocessor Mode
(
For 1- or 2-wait setting, external area access and multiplexed bus selection
Read timing
BCLK
CSi
ADi
/DBi
ADi
BHE
t
ALE
RD
Write timing
BCLK
CSi
ADi
/DBi
ADi
BHE
ALE
WR,WRL,
WRH
1
tcyc =
f(BCLK)
Measuring conditions :
V = 5 V
CC
Input timing voltage : V
Output timing voltage : V
Figure 1.21.8 Timing Diagram (7)
Rev.1.00 2003.05.30 page 256
t
d(BCLK-CS)
25ns.max
t
d(AD-ALE)
(0.5 ✕ tcyc-25)ns.min
Address
t
d(BCLK-AD)
25ns.max
d(BCLK-ALE)
t
h(BCLK-ALE)
25ns.max
-4ns.min
t
d(BCLK-RD)
t
d(BCLK-CS)
25ns.max
t
Address
t
d(AD-ALE)
(0.5 ✕ tcyc-25)ns.min
t
d(BCLK-AD)
25ns.max
t
d(BCLK-ALE)
t
h(BCLK-ALE)
25ns.max
-4ns.min
= 0.8 V, V = 2.0 V
IL IH
= 0.4 V, V = 2.4 V
OL OH
)
tcyc
t
h(ALE-AD)
(0.5 ✕ tcyc-15)ns.min
t
dZ(RD-AD)
8ns.max
t
ac3(RD-DB)
(1.5 ✕ tcyc-45)ns.max
t
d(AD-RD)
0ns.min
25ns.max
tcyc
d(BCLK-DB)
40ns.max
Data output
t
d(DB-WR)
(1.5 ✕ tcyc-40)ns.min
t
d(AD-WR)
0ns.min
t
d(BCLK-WR)
25ns.max
Electrical Characteristics
t
h(BCLK-CS)
t
h(RD-CS)
4ns.min
(0.5 ✕ tcyc-10)ns.min
Address
Data input
t
h(RD-DB)
t
SU(DB-RD)
0ns.min
40ns.min
t
h(BCLK-AD)
4ns.min
t
h(RD-AD)
(0.5 ✕ tcyc-10)ns.min
t
h(BCLK-RD)
0ns.min
t
h(BCLK-CS)
t
h(WR-CS)
(0.5 ✕ tcyc-10)ns.min
4ns.min
t
h(BCLK-DB)
4ns.min
Address
t
h(WR-DB)
(0.5 ✕ tcyc-10)ns.min
t
h(BCLK-AD)
4ns.min
t
h(WR-AD)
(0.5 ✕ tcyc-10)ns.min
t
h(BCLK-WR)
0ns.min