Precautions For Interrupts; Reading Address 00000; Sp Setting; Nmi Interrupt - Renesas M16C/60 Series Hardware Manual

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1.5 Precautions for Interrupts

1.5.1 Reading Address 00000

Do not read the address 00000
CPU reads interrupt information (interrupt number and interrupt request priority level) from the
address 00000
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If the address 00000
among the enabled interrupts is set to "0". This causes a problem that the interrupt is canceled, or an
unexpected interrupt is generated.

1.5.2 SP Setting

Set any value in the SP (USP, ISP) before accepting an interrupt. The SP (USP, ISP) is set to "0000
after reset. Therefore, if an interrupt is accepted before setting any value in the SP (USP, ISP), the
program may go out of control.
Especially when using NMI interrupt, set a value in the ISP at the beginning of the program. For the
first and only the first instruction after reset, all interrupts including NMI interrupt are disabled.
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1.5.3 NMI Interrupt

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1.
The NMI interrupt cannot be disabled. If this interrupt is unused, connect the NMI pin to V
resistor (pull-up).
2.
The input level of the NMI pin can be read by accessing the P8_5 bit of the P8 register. Note that the
P8_5 bit can only be read when determining the pin level in NMI interrupt routine.
3.
Stop mode cannot be entered into while input on the NMI pin is low. This is because while input on
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the NMI pin is low the CM10 bit of the CM1 register is fixed to "0".
4.
Do not go to wait mode while input on the NMI pin is low. This is because when input on the NMI pin
goes low, the CPU stops but CPU clock remains active; therefore, the current consumption in the
chip does not drop. In this case, normal condition is restored by an interrupt generated thereafter.
5.
The low and high level durations of the input signal to the NMI pin must each be 2 CPU clock cycles
+ 300 ns or more.
Rev.1.00
2003.05.30
page 5
16
in a program. When a maskable interrupt request is accepted, the
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during the interrupt sequence. At this time, the IR bit for the accepted interrupt is set to "0".
is read in a program, the IR bit for the interrupt which has the highest priority
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1.5 Precautions for Interrupts
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via a
CC
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