Renesas M16C/60 Series Hardware Manual page 77

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M16C/6N5 Group
Table 1.8.7 Allowed Transition and Setting
High-speed mode,
Middle-speed mode
Low-speed mode
(Note 2)
Low power
dissipation mode
PLL operation
mode (Note 2)
Ring oscillator
mode
Ring oscillator low power
dissipation mode
Stop mode
Wait mode
-: Cannot transit
Note 1: Avoid making a transition when the CM20 bit = 1 (oscillation stop,
re-oscillation detection function enabled). Set the CM20 bit to "0" (oscillation
stop, re-oscillation detection function disabled) before transiting.
Note 2: Ring oscillator clock oscillates and stops in low-speed mode. In this mode,
the ring oscillator can be used as peripheral function clock. Sub clock
oscillates and stops in PLL operation mode. In this mode, sub clock can
be used as peripheral function clock.
Note 3: PLL operation mode can only be entered from and changed to high-speed
mode.
Note 4: Set the CM06 bit to "1" (division by 8 mode) before transiting from ring
oscillator mode to high- or middle-speed mode.
Note 5: When exiting stop mode, the CM06 bit is set to "1" (division by 8 mode).
Note 6: If the CM05 bit is set to "1" (main clock stop), then the CM06 bit is set to "1"
(division by 8 mode).
Note 7: A transition can be made only when sub clock is oscillating.
Note 8: State transitions within the same mode (divide-by-n values changed or
sub clock oscillation turned on or off) are shown in the table below.
Sub clock oscillating
No Divided Divided Divided Divided No Divided Divided Divided Divided
division by 2 by 4 by 8 by 16 division by 2 by 4 by 8 by 16
No division (4)
Divided by 2 (3)
Divided by 4 (3) (4)
Divided by 8 (3) (4)
Divided by 16 (3) (4)
No division (2)
Divided by 2 - (2)
Divided by 4 -
Divided by 8 -
Divided by 16 -
Note 9: ( ):setting method. Refer to right table.
Rev.1.00 2003.05.30 page 63
High-speed mode, Low-speed Low power PLL operation Ring oscillator Ring oscillator
middle-speed mode
dissipation mode
mode (Note 2)
(9)
(Note 8)
(Note 7)
(8)
(Notes 1, 6)
- (10)
(12)
-
(Note 3)
(14)
-
(Note 4)
- -
(18)
(18)
(Note 5)
(18) (18)
Sub clock turned off
(5) (7) (6) (1)
(5) (7) (6) -
(7) (6) -
(5) (6) -
(5) (7) -
- - - -
- - - (3)
- (2) - - (3)
- - (2) - (3)
- - - (2) (3)
State after transition
mode
mode
(Note 2)
(13)
- (15)
(Note 3)
(11)
- -
- -
- -
- - (Note 8)
- - (10)
(18)
(18) -
(Note 5)
(18) - (18)
(1) CM04=0
(2) CM04=1
( 3) CM06=0
( 4) CM06=0
( 5) CM06=0
( 6) CM06=0
(7) CM06=1
(8) CM07=0
(9) CM07=1
(10) CM05=0
- - - -
(11) CM05=1
(1) - - -
(12) PLC07=0
- (1) - -
( 13) PLC07=1
- - (1) -
- - - (1)
(14) CM21=0
(4) (5) (7) (6)
( 15) CM21=1
(5) (7) (6)
(16) CM10=1
(4) (7) (6)
(17) WAIT
(4) (5) (6)
(18) Hardware
(4) (5) (7)
CM04, CM05, CM06, CM07:CM0 register's bits
CM10, CM11, CM16, CM17:CM1 register's bits
CM20, CM21
PLC07
Clock Generation Circuit
Stop
low power
mode
dissipation mode
(16)
-
(Note 1)
(16)
-
(Note 1)
(16)
-
(Note 1)
- -
(11) (16)
(Note 1) (Note 1)
(16)
(Note 8)
(Note 1)
(18)
(Note 5)
(18) -
Setting Operation
Sub clock turned off
Sub clock oscillating
CPU clock no division
CM17=0 mode
CM16=0
CPU clock division by 2
CM17=0 mode
CM16=1
CPU clock division by 4
CM17=1 mode
CM16=0
CPU clock division by 16
CM17=1 mode
CM16=1
CPU clock division by 8 mode
Main clock, PLL clock
or ring oscillator clock
selected
Sub clock selected
Main clock oscillating
Main clock turned off
Main clock selected
CM11=0
PLL clock selected
CM11=1
Main clock or
PLL clock selected
Ring oscillator clock selected
Transition to stop mode
Transition to wait mode
instruction
Exit stop mode or wait
interrupt mode
:CM2 register's bits
:PLC0 register's bit
Wait
mode
(17)
(17)
(17)
-
(17)
(17)
-