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M16C/6N5 Group
Table 1.7.5 Pin Functions for Each Processor Mode
Processor mode
PM05 to PM04 bits
Data bus width
BYTE pin
P0
to P0
0
7
P1
to P1
0
7
P2
0
P2
to P2
1
7
P3
0
P3
to P3
1
3
P3
to P3
PM11 = 0 A
4
7
PM11 = 1 I/O ports
P4
to P4
PM06 = 0 A
0
3
PM06 = 1 I/O ports
P4
CS0 = 0
4
CS0 = 1
P4
CS1 = 0
5
CS1 = 1
P4
CS2 = 0
6
CS2 = 1
P4
CS3 = 0
7
CS3 = 1
P5
PM02 = 0
0
PM02 = 1 - (Note 3)
P5
PM02 = 0
1
PM02 = 1 - (Note 3)
P5
2
P5
3
P5
4
P5
5
P5
6
P5
7
I/O ports: Function as I/O ports or peripheral function I/O pins.
Note 1: For setting the PM01 to PM00 bits to "01
"11
" (multiplexed bus assigned to the entire CS space), apply "H" to the BYTE pin (external data bus
2
is an 8-bit width). While the CNV
after reset. If the PM05 to PM04 bits are set to "11
P4
to P4
become I/O ports, in which case the accessible area for each CS is 256 bytes.
0
3
Note 2: In separate bus mode, these pins serve as the address bus.
Note 3:
If the data bus is 8-bit width, make sure the PM02 bit is set to "0" (RD, BHE, WR).
Note 4: When accessing the area that uses a multiplexed bus, these pins output an indeterminate value
during a write.
Rev.1.00
2003.05.30
page 37
Memory expansion mode or microprocessor mode
00
(separate bus)
2
8 bits
16 bits
"H"
"L"
D
to D
0
7
I/O ports
D
to D
8
15
A
0
A
to A
1
7
A
8
A
to A
9
11
to A
12
15
to A
16
19
I/O ports
______
CS
0
I/O ports
______
CS
1
I/O ports
______
CS
2
I/O ports
______
CS
3
_______
WR
________
WRL
________
BHE
_________
WRH
______
RD
BCLK
___________
HLDA
___________
HOLD
ALE
_________
RDY
2
pin is held "H" (V
SS
______
01
(CS
is for multiplexed bus and 11
2
2
others are for separate bus)
______
10
(CS
is for multiplexed bus and
2
1
others are for separate bus)
8 bits
"H"
D
to D
(Note 4)
0
7
I/O ports
D
A
/D
(Note 2) A
0
0
A
to A
/D
to D
A
1
7
1
7
(Note 2)
(Note 2)
A
________
- (Note 3)
WRL
_________
- (Note 3)
WRH
" (memory expansion mode) and the PM05 to PM04 bits to
_____
), do not rewrite the PM05 to PM04 bits to "11
CC1
" during memory expansion mode, P3
2
Memory expansion mode
(multiplexed bus
2
for the entire space)
(Note 1)
16 bits
8 bits
"L"
"H"
I/O ports
to D
(Note 4) I/O ports
8
15
A
/D
0
0
0
to A
/D
to D
A
to A
/D
1
7
0
6
1
7
/D
(Note 2) A
8
7
8
I/O ports
I/O ports
I/O ports
- (Note 3)
- (Note 3)
to P3
1
_____
_____
________ ______
Bus Control
to D
1
7
"
2
and
7
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