Renesas M16C/60 Series Hardware Manual page 258

Under development
This document is under development and its contents are subject to change.
M16C/6N5 Group
Timing Requirements
(Referenced to V = 5 V, V
CC
Table 1.21.7 External Clock Input (X
Symbol
External clock input cycle time
t
C
t External clock input HIGH pulse width
w(H)
External clock input LOW pulse width
t
w(L)
t External clock rise time
r
t External clock fall time
f
Table 1.21.8 Memory Expansion Mode and Microprocessor Mode
Symbol
t Data input access time (for setting with no wait)
ac1(RD-DB)
Data input access time (for setting with wait)
t
ac2(RD-DB)
t Data input access time (when accessing multiplexed bus area)
ac3(RD-DB)
t Data input setup time
su(DB-RD)
________
t RDY input setup time
su(RDY-BCLK)
__________
t
HOLD input setup time
su(HOLD-BCLK)
t Data input hold time
h(RD-DB)
________
t
RDY input hold time
h(BCLK-RDY)
__________
t HOLD input hold time
h(BCLK-HOLD)
__________
t
HLDA output delay time
d(BCLK-HLDA)
Note 1: Calculated according to the BCLK frequency as follows:
0.5 ✕ 10
9
– 45 [ns]
f(BCLK)
Note 2: Calculated according to the BCLK frequency as follows:
(n –0.5) ✕ 10
f(BCLK)
Note 3: Calculated according to the BCLK frequency as follows:
(n –0.5) ✕ 10
f(BCLK)
Rev.1.00 2003.05.30 page 244
= 0 V, at Topr = –40 to 85 °C unless otherwise specified)
SS
Input)
IN
Parameter
Parameter
9
– 45 [ns] n is "2" for 1-wait setting, "3" for 2-wait setting and "4" for 3-wait setting.
9
– 45 [ns] n is "2" for 2-wait setting, "3" for 3-wait setting.
Electrical Characteristics
Standard
Unit
Min. Max.
62.5 ns
25 ns
25 ns
15
ns
15 ns
Standard
Unit
Min.
Max.
(Note 1)
ns
(Note 2) ns
(Note 3)
ns
40 ns
ns
30
40 ns
0 ns
0 ns
0 ns
40
ns