Renesas M16C/60 Series Hardware Manual page 53

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M16C/6N5 Group
Table 1.7.7 Software Wait Related Bits and Bus Cycles
PM2 Register
Area Bus mode
PM20 bit
SFR
-
-
Internal
-
ROM, RAM
-
External
Separate
area
bus
Multiplexed
bus
(Note 2)
________
Note 1: To use the RDY signal, set this bit to "0 ".
Note 2: To access in multiplexed bus mode, set the corresponding bit of CS0W to CS3W to "0" (with wait state).
Note 3: After reset, the PM17 bit is set to "0" (without wait state), all of the CS0W to CS3W bits are set to "0"
(with wait state), and the CSE register is set to "00
internal RAM and internal ROM are accessed with no wait state, and all external areas are
accessed with one wait state.
Note 4: When the selected CPU clock source is the PLL clock, the number of wait cycles can be altered by
the PM20 bit in the PM2 register. When using a 16 MHz or higher PLL clock, be sure to set the PM20
bit to "0" (2 wait cycles).
Rev.1.00 2003.05.30 page 39
CSR register
CS3W bit (Note 1)
PM1 Register
CS2W bit (Note 1)
PM17 bit
CS1W bit (Note 1)
CS0W bit (Note 1)
0 - -
1 - -
- 0 -
- 1 -
- 0 1
- - 0
- - 0
- 0
-
1
- 1
- 0
-
-
- 0
-
- 0
- 1 0
CSE register
CS31W to CS30W bits
Software
CS21W to CS20W bits
wait
CS11W to CS10W bits
CS01W to CS00W bits
- -
- -
- No wait
- 1 wait
00 No wait
2
00 1 wait
2
01 2 waits
2
10 3 waits
2
1 wait
00
2
00 1 wait
2
2 waits
01
2
3 waits
10
2
00 1 wait
2
______
" (one wait state for CS
16
Bus Control
Bus cycle
2 BCLK cycles (Note 4)
3 BCLK cycles (Note 4)
1 BCLK cycle (Note 3)
2 BCLK cycles
1 BCLK cycle (read)
2 BCLK cycles (write)
2 BCLK cycles (Note 3)
3 BCLK cycles
4 BCLK cycles
2 BCLK cycles
3 BCLK cycles
3 BCLK cycles
4 BCLK cycles
3 BCLK cycles
______
to CS ). Therefore, the
0 3