Table of Contents
Advertisement
Under development
This document is under development and its contents are subject to change.
M16C/6N5 Group
1.8 Precautions for Serial I/O (Clock Synchronous Serial I/O Mode)
1.8.1 Transmission/reception
1.
With an external clock selected, and choosing the RTS function, the output level of the RTS
goes to "L" when the data-receivable status becomes ready, which informs the transmission side
that the reception has become ready. The output level of the RTS
starts. So if the RTS
transmission and reception data with consistent timing. With the internal clock, the RTS function
has no effect.
2.
If a low-level signal is applied to the NMI pin when the IVPCR1 bit = 1 (three-phase output forcible
cutoff by input on NMI pin enabled) of the TB2SC register, the RTS
impedance state.
1.8.2 Transmission
When an external clock is selected, the conditions must be met while if the CKPOL bit of the UiC0
register = 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of
the transfer clock), the external clock is in the high state; if the CKPOL bit of the UiC0 register = 1
(transmit data output at the rising edge and the receive data taken in at the falling edge of the transfer
clock), the external clock is in the low state.
• The TE bit of the UiC1 register = 1 (transmission enabled)
• The TI bit of the UiC1 register = 0 (data present in UiTB register)
_______
• If CTS function is selected, input on the CTS
1.8.3 Reception
1. In operating the clock synchronous serial I/O, operating a transmitter generates a shift clock.
Fix settings for transmission even when using the device only for reception. Dummy data is output
to the outside from the TxD
2. When an internal clock is selected, set the TE bit of the UiC1 register to "1" (transmission enabled)
and write dummy data to the UiTB register, and the shift clock will thereby be generated. When an
external clock is selected, set the TE bit to "1" and write dummy data to the UiTB register, and the
shift clock will be generated when the external clock is fed to the CLK
3. When successively receiving data, if all bits of the next receive data are prepared in the UARTi
receive register while the RI bit of the UiC1 register = 1 (data present in the UiRB register), an
overrun error occurs and the OER bit of the UiRB register is set to "1" (overrun error occurred). In
this case, because the content of the UiRB register is indeterminate, a corrective measure must be
taken by programs on the transmit and receive sides so that the valid data before the overrun error
occurred will be retransmitted. Note that when an overrun error occurred, the IR bit of the SiRIC
register does not change state.
4. To receive data in succession, set dummy data in the lower-order byte of the UiTB register every
time reception is made.
5. When an external clock is selected, the conditions must be met while if the CKPOL bit = 0, the
external clock is in the high state; if the CKPOL bit = 1, the external clock is in the low state.
• The RE bit of the UiC1 register = 1 (reception enabled)
• The TE bit of the UiC1 register = 1 (transmission enabled)
• The TI bit of the UiC1 register = 0 (data present in the UiTB register)
Rev.1.00
2003.05.30
page 14
1.8 Precautions for Serial I/O (Clock Synchronous Serial I/O Mode)
pin is connected to the CTS
i
_______
_______
_______
(i = 0 to 2) pin when receiving data.
i
_______
pin goes to "H" when reception
i
________
pin on the transmission side, the circuit can
i
________
pin = L
i
_______
and CLK
pins go to a high-
2
2
input pin.
i
pin
i
Advertisement
Chapters
Table of Contents
